You are here
ARIES DESIGN AUTOMATION, LLC
UEI: KHN1ZN6ALMV4
# of Employees: 2
HUBZone Owned: No
Socially and Economically Disadvantaged: No
Woman Owned: No
Award Charts
Award Listing
-
Design and Formal Verification of a Fault-Tolerant RISC-V Processor Core Augmented to Accelerate Image and Science Data Processing
Amount: $150,000.00In this SBIR Phase I project, we will design and formally verify a fault-tolerant processor core implementing the RISC-V Instruction Set Architecture (ISA), augmented with arrays of reconfigurable pro ...
SBIRPhase I2022National Aeronautics and Space Administration -
Design and Formal Verification of a RISC-V DSP for Space Communication
Amount: $1,000,000.00In this SBIR Direct to Phase II project, we will design and formally verify a reconfigurable pipelined Digital Signal Processor (DSP) that will implement the free open-source RISC-V Instruction Set Ar ...
SBIRPhase II2021Department of Defense Air Force -
Scalable Parallel Algorithms for Formal Verification of Software
Amount: $125,000.00We will develop an efficient Graphics Processing Unit (GPU) based parallel Binary Decision Diagram (BDD) software package, and will also combine it with our GPU-based parallel SAT solver that we are c ...
SBIRPhase I2013National Aeronautics and Space Administration -
Formal Verification of Interactions of the RTOS, Memory System, and Application Programs at the PowerPC 750 Binary Code Level
Amount: $125,000.00In the proposed project, we will formally verify the correctness of the interaction between a Real-Time Operating System (RTOS) and user processes under various operating scenarios, such as multitaski ...
SBIRPhase I2013National Aeronautics and Space Administration -
Scalable Parallel Algorithms for Formal Verification of Software
Amount: $125,000.00We will develop a prototype of a GPU-based parallel Binary Decision Diagram (BDD) software package. BDDs are a data structure that satisfies some simple restrictions, resulting in a unique representat ...
SBIRPhase I2012National Aeronautics and Space Administration -
Using Automated Abstractions to Classify System States for Software Health Monitoring
Amount: $90,000.00In most critical software systems, a state that is partially visible through values passed across interfaces contains information that could determine the health of the software system, and whether a ...
SBIRPhase I2011Department of Commerce National Institute of Standards and Technology -
Reconfigurable VLIW Processor for Software Defined Radio
Amount: $600,000.00We will implement an environment for design, formal verification, compilation of code, and performance and power evaluation of Systems on a Chip (SOCs) consisting of heterogeneous processor cores that ...
SBIRPhase II2011National Aeronautics and Space Administration -
Reconfigurable VLIW Processor for Software Defined Radio
Amount: $100,000.00We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the PowerPC 750 Instruction Set Architectur ...
SBIRPhase I2010National Aeronautics and Space Administration -
An Efficient Parallel SAT Solver Exploiting Multi-Core Environments
Amount: $600,000.00The hundreds of stream cores in the latest graphics processors (GPUs), and the possibility to execute non-graphics computations on them, open unprecedented levels of parallelism at a very low cost. In ...
SBIRPhase II2010National Aeronautics and Space Administration -
SBIR Phase I: Automatic Formal Verification of Chip-Multi-Threaded Multicore Processors
Amount: $150,000.00This Small Business Innovation Research (SBIR) Phase I project will result in an efficient and scalable method for design and formal verification of Chip-Multi-Threaded multicore processors, where the ...
SBIRPhase I2010National Science Foundation