We proposed a simple wafer scale method to leap frog current CMOS technology. The slow-down in CMOS scaling is limited by technology difficulties and by economics. In tooling up for .13-micron technology, the jump from .18-micron is costing $10 billionis equipment alone, plus accompanying expenses… More

"We intend to increase by an order of magnitude, the current density of silicon-based tunnel diodes. This increase directly relates to a corresponding increase in performance (speed). Apart from being the fastest of all microelectronic devices, tunneldiodes (TDs) have negative differential… More

"We propose to combine the technologies of SOI manufacture with strain-inducing wafer bonding to produce Strained-Si On Insulator (SSOI) wafers. Optimizing this new Strained-Silicon-on-Insulator will increase carrier mobilities by a factor of at least x3,lower the band gap by 20%, and reduce… More

We propose to increase the mobility of both n- and p-type GaN by applying tensile strain and fixing the strain by bonding to an appropriate heat sink material. Straining in other semiconductor materials is now recognized as a viable route to higherperformance. We have demonstrated in these systems… More

This Small Business Innovation Research (SBIR) Phase I propose to combine the technologies of silicon-on-insulator (SOI) manufacture with strain-inducing wafer bonding to produce Strained-Si On Insulator (SSOI) wafers. Silicon-based devices with silicon/germanium (Si/Ge) heterostructures have… More

This Small Business Innovative Research Phase II project will develop a process that integrates wafer bonding technology with a novel straining process to create a new ultra fast silicon substrate: Strained-Silicon-On-Insulator (SSOI). This substrate can undergo normal IC fabrication and resulting… More