In this research we will develop a system level tool to translate binary code of a general-purpose processor into Register Transfer Level VHDL code to be mapped onto FPGA-based reconfigurable hardware. We further plan to study techniques for performing hardware/software co-design on integrated… More

This Small Business Innovation Research (SBIR) Phase I project develops an automated compiler to translate software binary and assembly code of a general-purpose DSP processor into Register Transfer Level VHDL and Verilog code for subsequent mapping onto FPGA hardware. Recent advances in embedded… More

NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically… More

Many DOD systems require advanced digital signal processing and image processing functions that cannot be efficiently implemented on conventional micro-processors, hence designers have started mapping these applications onto FPGAs. However, most FPGA implementations are manually designed and highly… More

NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically… More

Many DOD systems require high-performance digital signal processing and image processing functions that cannot be implemented efficiently on conventional microprocessors. Systems engineers often address these issues by mapping the compute-intensive portions of these applications onto FPGAs in the… More

Commercial FPGA programming software tools use logic synthesis tools to route the connections between logic gates, look-up tables, and memory units. Current commercial tools, however, are optimized to maximize operation speed and minimize area and memory utilization. This proposal addresses the… More