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Company Information:

Company Name:
BINACHIP, INC.
Address:
203 N. Wabash Av.
SUITE 203
Chicago, IL 60601
Phone:
(847) 757-8708
URL:
N/A
EIN:
200067604
DUNS:
134656532
Number of Employees:
3
Woman-Owned?:
No
Minority-Owned?:
No
HUBZone-Owned?:
No

Commercialization:

Has been acquired/merged with?:
N/A
Has had Spin-off?:
N/A
Has Had IPO?:
N/A
Year of IPO:
N/A
Has Patents?:
N/A
Number of Patents:
N/A
Total Sales to Date $:
$ 0.00
Total Investment to Date $
$ 0.00
POC Title:
N/A
POC Name:
N/A
POC Phone:
N/A
POC Email:
N/A
Narrative:
N/A

Award Totals:

Program/Phase Award Amount ($) Number of Awards
SBIR Phase I $337,933.00 4
SBIR Phase II $1,349,500.00 2
STTR Phase I $100,000.00 1

Award List:

A System Level Tool for Translating Software to Reconfigurable Hardware

Award Year / Program / Phase:
2005 / STTR / Phase I
Award Amount:
$100,000.00
Agency:
NASA
Principal Investigator:
Research Institution:
University of Illinois at Chicago
RI Contact:
Prith Banerjee
Abstract:
In this research we will develop a system level tool to translate binary code of a general-purpose processor into Register Transfer Level VHDL code to be mapped onto FPGA-based reconfigurable hardware. We further plan to study techniques for performing hardware/software co-design on integrated… More

SBIR Phase I: Automated Design Environment for Embedded Systems

Award Year / Program / Phase:
2006 / SBIR / Phase I
Award Amount:
$100,000.00
Agency:
NSF
Principal Investigator:
Abstract:
This Small Business Innovation Research (SBIR) Phase I project develops an automated compiler to translate software binary and assembly code of a general-purpose DSP processor into Register Transfer Level VHDL and Verilog code for subsequent mapping onto FPGA hardware. Recent advances in embedded… More

A Hardware/Software Design Environment for Reconfigurable Communication Systems

Award Year / Program / Phase:
2006 / SBIR / Phase I
Award Amount:
$69,300.00
Agency:
NASA
Principal Investigator:
David Zaretsky, Principal Investigator
Abstract:
NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically… More

A High Level Synthesis Tool for FPGA Design from Software Binaries

Award Year / Program / Phase:
2007 / SBIR / Phase I
Award Amount:
$98,640.00
Agency / Branch:
DOD / DARPA
Principal Investigator:
David Zaretsky, Senior Software Engineer
Abstract:
Many DOD systems require advanced digital signal processing and image processing functions that cannot be efficiently implemented on conventional micro-processors, hence designers have started mapping these applications onto FPGAs. However, most FPGA implementations are manually designed and highly… More

A Hardware/Software Design Environment for Reconfigurable Communication Systems

Award Year / Program / Phase:
2007 / SBIR / Phase II
Award Amount:
$600,000.00
Agency:
NASA
Principal Investigator:
David T. Zaretsky, Principal Investigator
Abstract:
NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically… More

A High Level Synthesis Tool for FPGA Design from Software Binaries

Award Year / Program / Phase:
2009 / SBIR / Phase II
Award Amount:
$749,500.00
Agency / Branch:
DOD / DARPA
Principal Investigator:
Abstract:
Many DOD systems require high-performance digital signal processing and image processing functions that cannot be implemented efficiently on conventional microprocessors. Systems engineers often address these issues by mapping the compute-intensive portions of these applications onto FPGAs in the… More

FPGA Low Power Design Rules

Award Year / Program / Phase:
2010 / SBIR / Phase I
Award Amount:
$69,993.00
Agency / Branch:
DOD / ARMY
Principal Investigator:
David Zaretsky, Chief Executive Officer
Abstract:
Commercial FPGA programming software tools use logic synthesis tools to route the connections between logic gates, look-up tables, and memory units. Current commercial tools, however, are optimized to maximize operation speed and minimize area and memory utilization. This proposal addresses the… More