USA flag logo/image

An Official Website of the United States Government

Company Information:

Company Name: BINACHIP, INC.
City: Chicago
State: IL
Zip+4: 60601
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
Website URL: N/A
Phone: (847) 757-8708

Award Totals:

Program/Phase Award Amount ($) Number of Awards
SBIR Phase I $337,933.00 4
SBIR Phase II $1,349,500.00 2
STTR Phase I $100,000.00 1

Award List:

A System Level Tool for Translating Software to Reconfigurable Hardware

Award Year / Program / Phase: 2005 / STTR / Phase I
Agency: NASA
Research Institution: University of Illinois at Chicago
Principal Investigator: Prith Banerjee
Award Amount: $100,000.00
RI Contact: Prith Banerjee
Abstract:
In this research we will develop a system level tool to translate binary code of a general-purpose processor into Register Transfer Level VHDL code to be mapped onto FPGA-based reconfigurable hardware. We further plan to study techniques for performing hardware/software co-design on integrated… More

SBIR Phase I: Automated Design Environment for Embedded Systems

Award Year / Program / Phase: 2006 / SBIR / Phase I
Agency: NSF
Principal Investigator: David Zaretsky, Dr
Award Amount: $100,000.00
Abstract:
This Small Business Innovation Research (SBIR) Phase I project develops an automated compiler to translate software binary and assembly code of a general-purpose DSP processor into Register Transfer Level VHDL and Verilog code for subsequent mapping onto FPGA hardware. Recent advances in embedded… More

A Hardware/Software Design Environment for Reconfigurable Communication Systems

Award Year / Program / Phase: 2006 / SBIR / Phase I
Agency: NASA
Principal Investigator: David Zaretsky, Principal Investigator
Award Amount: $69,300.00
Abstract:
NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically… More

A High Level Synthesis Tool for FPGA Design from Software Binaries

Award Year / Program / Phase: 2007 / SBIR / Phase I
Agency / Branch: DOD / DARPA
Principal Investigator: David Zaretsky, Senior Software Engineer
Award Amount: $98,640.00
Abstract:
Many DOD systems require advanced digital signal processing and image processing functions that cannot be efficiently implemented on conventional micro-processors, hence designers have started mapping these applications onto FPGAs. However, most FPGA implementations are manually designed and highly… More

A Hardware/Software Design Environment for Reconfigurable Communication Systems

Award Year / Program / Phase: 2007 / SBIR / Phase II
Agency: NASA
Principal Investigator: David T. Zaretsky, Principal Investigator
Award Amount: $600,000.00
Abstract:
NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically… More

A High Level Synthesis Tool for FPGA Design from Software Binaries

Award Year / Program / Phase: 2009 / SBIR / Phase II
Agency / Branch: DOD / DARPA
Principal Investigator: David Zaretsky, CEO
Award Amount: $749,500.00
Abstract:
Many DOD systems require high-performance digital signal processing and image processing functions that cannot be implemented efficiently on conventional microprocessors. Systems engineers often address these issues by mapping the compute-intensive portions of these applications onto FPGAs in the… More

FPGA Low Power Design Rules

Award Year / Program / Phase: 2010 / SBIR / Phase I
Agency / Branch: DOD / ARMY
Principal Investigator: David Zaretsky, Chief Executive Officer
Award Amount: $69,993.00
Abstract:
Commercial FPGA programming software tools use logic synthesis tools to route the connections between logic gates, look-up tables, and memory units. Current commercial tools, however, are optimized to maximize operation speed and minimize area and memory utilization. This proposal addresses the… More