USA flag logo/image

An Official Website of the United States Government

A Hardware/Software Design Environment for Reconfigurable Communication Systems

Award Information

Agency:
National Aeronautics and Space Administration
Branch:
N/A
Award ID:
77664
Program Year/Program:
2006 / SBIR
Agency Tracking Number:
053196
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
BINACHIP, INC.
203 N. Wabash Av. SUITE 203 Chicago, IL 60601
View profile »
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 1
Fiscal Year: 2006
Title: A Hardware/Software Design Environment for Reconfigurable Communication Systems
Agency: NASA
Contract: NNC06CA60C
Award Amount: $69,300.00
 

Abstract:

NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically develop flexible, reconfigurable communications systems. We will develop automated compiler algorithms to translate software code available in a variety of high level languages (C/C++/SIMULINK) and assembly of various general purpose processors into Register Transfer Level VHDL code to be mapped onto FPGA-based hardware. We further plan to study techniques for performing hardware/software co-design on integrated systems-on-a-chip platforms consisting of embedded processors, memories and FPGAs. We will demonstrate our concepts using a prototype compiler that will translate software implementations of communications applications into a hardware/software implementation on a Xilinx Virtex II Pro Platform FPGA and a DINI DN2000k10 board. The proposed work is revolutionary and addresses NASA's Space Exploration needs as follows: (1) it will develop a system level tool for designing hardware systems which will reduce design times from months to days (2) it will enable the use of cost-efficient, high-performance FPGAs (3) it will allow engineers to reuse of millions of lines of software developed in the past for general purpose processors, and migrate them painlessly to newer SOC pla

Principal Investigator:

David Zaretsky
Principal Investigator
8477578708
dcz@northwestern.edu

Business Contact:

Prith Banerjee
Chairman and Chief Scientist
8477578708
prith@uic.edu
Small Business Information at Submission:

Binachip, Inc.
2130 Chandler Lane Glenview, IL 60026

EIN/Tax ID: 200067604
DUNS: N/A
Number of Employees:
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No