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A System Level Tool for Translating Software to Reconfigurable Hardware
- Small Business Information
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Woman-Owned: NoMinority-Owned: NoHUBZone-Owned: No
- Phase 1
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Fiscal Year: 2005Title: A System Level Tool for Translating Software to Reconfigurable HardwareAgency: NASAContract: NNA05AC26CAward Amount: $100,000.00
Abstract:
In this research we will develop a system level tool to translate binary code of a general-purpose processor into Register Transfer Level VHDL code to be mapped onto FPGA-based reconfigurable hardware. We further plan to study techniques for performing hardware/software co-design on integrated systems-on-a-chip platforms consisting of embedded processors, memories and FPGAs. Finally we will develop techniques to perform area, delay and power tradeoffs in the hardware that is synthesized by our compiler on the FPGAs. We will demonstrate our concepts using a prototype compiler that will translate binary code of a Texas Instrument TMS320 C6000 processor into a hardware/software implementation on a Xilinx Virtex II Pro Platform FPGA. This work will be performed jointly between BINACHIP, a small business company, and University of Illinois at Chicago, a partner research institutionSmall Business Information at Submission:Research Institution Information:Binachip, Inc.
2130 Chandler Lane Glenview, IL 60026EIN/Tax ID: 200067604DUNS: N/ANumber of Employees:Woman-Owned: NoMinority-Owned: NoHUBZone-Owned: NoUniversity of Illinois at Chicago
851 South Morgan St.
Chicago, IL 60607Contact: Prith BanerjeeContact Phone: (847) 757-8708RI Type: Nonprofit college or university
Award Information
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Agency: National Aeronautics and Space Administration |
Branch: N/A |
Award ID: 76742 |
Program Year/Program: 2005 / STTR |
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Agency Tracking Number: 040009 |
Solicitation Year: N/A |
Solicitation Topic Code: N/A |
Solicitation Number: N/A |