A Hardware/Software Design Environment for Reconfigurable Communication Systems
NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically develop flexible, reconfigurable communications systems. We will develop automated compiler algorithms to translate software code available in a variety of high level languages (C/C++/SIMULINK) and assembly of various general purpose processors into Register Transfer Level VHDL code to be mapped onto FPGA-based hardware. We further plan to study techniques for performing hardware/software co-design on integrated systems-on-a-chip platforms consisting of embedded processors, memories and FPGAs. We will demonstrate our concepts using a prototype compiler that will translate software implementations of communications applications into a hardware/software implementation on a Xilinx Virtex II Pro Platform FPGA and a Digilent XUP FPGA board. The proposed work is revolutionary and addresses NASA's Space Exploration needs as follows: (1) it will develop a system level tool for designing hardware systems which will reduce design times from months to days (2) it will enable the use of cost-efficient, high-performance FPGAs (3) it will allow engineers to reuse of millions of lines of software developed in the past for general purpose processors, and migrate them painlessly to newer SOC platforms.
Small Business Information at Submission:
David T. Zaretsky
Prith F. Banerjee
Chairman and Chief Scientist
203 N Wabash, Suite 604 Chicago, IL 60601
Number of Employees: