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SCHEDULING TECHNOLOGY FOR SEMICONDUCTOR FABRICATION

Award Information

Agency:
National Science Foundation
Branch:
N/A
Award ID:
7481
Program Year/Program:
1988 / SBIR
Agency Tracking Number:
7481
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
Caps Logistics, Inc.
2700 Cumberland Parkway Atlanta, GA 30339
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Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 1
Fiscal Year: 1988
Title: SCHEDULING TECHNOLOGY FOR SEMICONDUCTOR FABRICATION
Agency: NSF
Contract: N/A
Award Amount: $50,000.00
 

Abstract:

MINIATURIZATION OF ELECTRONIC COMPONENTS INTO INTEGRATED CIRCUITS (SEMICONDUCTOR DEVICES) HAS DRAMATICALLY AFFECTED OUR LIVES. NO WHERE IS THIS MORE APPARENT THAN THE LARGE DEPENDENCY AMERICAN MANUFACTURING HAS ON SEMICONDUCTOR DESIGN AND FABRICATION. THE PRODUCTION OF AN INTEGRATED CIRCUIT REQUIRES A FOUR STAGE PROCESS: 1) WAFER FABRICATION; 2) WAFER PROBE; 3) ASSEMBLY (PACKAGING); AND 4) FINAL TEST. BECAUSE OF THE HIGH CAPITAL COSTS AND FAIRLY LOW VARIABLE RATE PRODUCTION COSTS, MANUFACTURERS OF SEMICONDUCTORS TRY TO MAINTAIN HIGH UTILIZATION OF THE WAFER FABRICATION EQUIPMENT. THE PROPOSED RESEARCH FOCUSES ON THE TASK OF EFFECTIVELY GENERATING SCHEDULES WHICH IMPROVE PERFORMANCE OF THE PRODUCTION SYSTEM. WITH A SMALL NUMBER OF BOTTLENECK PROCESSES DOMINATING THE SCHEDULE, IT IS REASONABLE TO EXPECT THAT CONCEPTS SUCH AS AGGREGATIONAND DECOMPOSITION CAN BE APPLIED TO REDUCE THE ORIGINAL PROBLEM TO ONE WHICH ESSENTIALLY INVOLVES ONLY THE BOTTLENECK PROCESSES. THEN, GIVEN A SOLUTION TO THE SIMPLERPROBLEM, TECHNIQUES OF DISAGGREGATION CAN BE APPLIED TO "EXPLODE" THE SOLUTION INTO THE FULL SCHEDULE.

Principal Investigator:

Dr christopher b lofgren
0

Business Contact:

Small Business Information at Submission:

Computer Aided Planning & Sche
2900 Paces Ferry Road Suite D-100 Atlanta, GA 30339

EIN/Tax ID:
DUNS: N/A
Number of Employees: N/A
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No