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Non-uniform Correction Algorithm Suite (NUCAS)

Award Information
Agency: Department of Defense
Branch: Army
Contract: W15P7T-06-C-F802
Agency Tracking Number: A043-125-1335
Amount: $729,909.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: A04-125
Solicitation Number: 2004.3
Timeline
Solicitation Year: 2004
Award Year: 2005
Award Start Date (Proposal Award Date): 2005-12-08
Award End Date (Contract End Date): 2007-11-30
Small Business Information
625 Mount Auburn Street
Cambridge, MA 02138
United States
DUNS: 115243701
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Mark Stevens
 Principal Scientist
 (617) 491-3474
 mstevens@cra.com
Business Contact
 Paul Gonsalves
Title: Vice President
Phone: (617) 491-3474
Email: pgonsalves@cra.com
Research Institution
N/A
Abstract

Image noise is often a limiting factor in target detection and recognition using infrared cameras. Many techniques exist for limiting temporal noise, but the predominant solution for fixed pattern noise correction is radiometric non-uniformity correction (NUC). This adds moving parts to the camera design and requires taking the camera off-line every 10 minutes or so during operation. Our proposed scene-based (SB) NUC alternative uses real-time image processing to perform NUC continuously during normal camera operation. In Phase I we prototyped the best known SBNUC algorithms and evaluated them on video sequences exhibiting widely varying fixed pattern and temporal noise. We also characterized their performance as a function of image motion (due to camera or scene motion). Consequently, we identified the optimal operating conditions for three types of SBNUC algorithms: constant statistics, motion compensated temporal filtering, and spatial filtering. In Phase II we propose to develop image analysis algorithms capable of determining the camera’s current operating condition in real-time, and hence specifying the most effective SBNUC to use for each video frame. Through our partner Nova Sensors, our algorithm suite will be implemented as an FPGA-accelerated dedicated image processor for NVESD’s SE-IR cameras, enabling extensive system evaluations outside laboratory environments.

* Information listed above is at the time of submission. *

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