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Firmware Analysis Test System

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00178-04-C-3024
Agency Tracking Number: N032-0481
Amount: $99,797.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N03-213
Solicitation Number: 2003.2
Timeline
Solicitation Year: 2003
Award Year: 2004
Award Start Date (Proposal Award Date): 2003-11-26
Award End Date (Contract End Date): 2005-04-17
Small Business Information
3272 Silver Pine Trail
Colorado Springs, CO 80920
United States
DUNS: 131860632
HUBZone Owned: No
Woman Owned: Yes
Socially and Economically Disadvantaged: No
Principal Investigator
 Lawrence Scally
 President
 (719) 266-6062
 lscally@adelphia.net
Business Contact
 Nancy Badenhop
Title: Chief Operating Officer
Phone: (719) 266-6062
Email: nbadenhop@adelphia.net
Research Institution
N/A
Abstract

Colorado Engineering, Inc (CEI) is a small woman owned business with a wealth of engineering expertise in the development of ASICs, boards, software and systems for DOD combat, weapon and sensor systems. Timing critical firmware dependent systems, require state-of-the-art analysis tools for debug, timing analysis, modification, performance evaluation, utilization evaluation, etc. These tools would be invaluable in all phases of the program: development, production, installation and maintenance. They are rarely thought of in the development phases, but in the installation and maintenance phases the need is apparent. In Phase I of the proposed effort, CEI will complete the design of a firmware analysis test system for multi-processor systems. Proposed Phase I objectives include: discussions and reviews with the Navy project sponsors, meetings with Lockheed Martin Moorestown engineers, detailed system architecture design, detailed software architecture design, detailed hardware architecture design, hardware and software cost analysis, operating environment analysis, and development of a detailed Phase II plan. The Firmware Analysis Test System (FATS) will allow for detailed monitoring and analysis of multi-processor systems

* Information listed above is at the time of submission. *

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