300 mm High Density Temperature Probe Card for Wafer- Level Reliability Testing
Agency / Branch:
DOC / NIST
Historical methods of reliability assessment are less and less effective as device sizes shrink. Already researchers are unable to package the many advanced devices because the act of cutting the wafer and the packaging operation pre-stresses or destroys the devices resulting in unreliable test results. Additionally the increasing cost of fabricating a wafer with advanced integrated circuit technology requires the designer to maximize the utilization of the wafer real estate. Additionally smaller devices require electrical characteristics and the short term and long term reliability to be know with even higher precision and accuracy. This is a proposal to design a probe card for massively parallel reliability testing to address this need. The objective of the project is to design a 300mm probe card with 5000 probes at sustained operating temperatures up to 400?C. The probes need to contact 50µm pad sizes that are typical in the industry. Additionally, the probes need to align to the pads throughout an operating envelope of 25?C to 400?C, contacting the pads after the system achieves thermal equilibrium.
Small Business Information at Submission:
Principal Investigator:Bryan Root
Celadon Systems Inc.
14763 Energy Way Apple Valley, MN 55124
Number of Employees: