Tape recorders presently used as spaceborne mass storage devices have a history of being unreliable and require extensive and costly ground testing to provide the confidence necessary to pass launch readiness. even then they do not always adequately perform their function on orbit. the objectie of… More

Seakr engineering, inc. will develop and demonstrate a solid state aircraft voice and data recorder design which will use both data encryption and data compression. the first part of the effort will be devoted to evaluating available off the shelf hardware and algorithms which can be used to perform… More

Most spacecraft require a memory to store data prior to the transmission of the data to an earth station. Until recently, the majority of spacecraft data storage requirements were provided by tape recorders. In 1989, however, a new era in spacecraft data storage began when SEAKR Engineering… More

The airborne reconnaissance community currently utilizes tape based storage technology. While this technology is proven, it still suffers from low mean time between failure (MTBF) and substandard data throughput rates. Additionally, with the introduction of state-of-the-art sensor platforms, it… More

The airborne reconnaissance community currently utilizes tape based storage technology. While this technology is proven, it still suffers from low mean time between failure (MTBF) and substandard data throughput rates. Additionally, with the introduction of state-of-the-art sensor platforms, it… More

In this first phase of technical development, this proposal for research and development seeks to design an architecture that will enable MIL-STD-1553B digital data bus monitoring through an isochronous channel of an IEEE-1394A High Performance Serial Bus.The traits of this design will give I&T… More

"A low power, low volume, realtime image processor using a re-configurable FPGA based processor design. The flexibility of general purpose processors are blended with the speed of ASICs to accomplish very high performance image processing using FPGA's.Data compression, Automatic target recognition… More

Target discrimination is the ability to select a desired target in the presence of multiple targets. Unfortunately, current passive infrared (IR) missile sensors are not adequate to discriminate between decoys, penetration aids, and targets based upon anindividual sensor signature. Acquiring a… More

The MIL-STD-1553B Bus is a widely supported data bus for avionics applications and compatible with most of the avionics equipment. However, its low data rate (1 Mbps) and command-response architecture are not suitable for many modern applications such as on-board autonomy. Therefore, the avionics… More

Reconfigurable computing offers high performance and adaptability for missile C4I applications, by merging the speed of custom digital circuits with the flexibility of software. Recent improvements have been made in development environments for reconfigurable computing, which allow designers to use… More

Present space based memory storage system technology cannot accommodate the performance requirements of some future missions. Three critical areas need to be addressed in order to bring the next generation memory system to fruition. These areas are power, storage density, and backplane speed.… More

The objective of this project is to develop a space qualified bulk memory system that focuses on reducing weight, power, volume and cost of existing memory systems while increasing memory capacity and input data rates to meet requirements of future military and commercial space applications. This… More

On-board processing in satellites and spacecraft has been severely limited by the lack of space-qualified, High-Performance Computing (HPC) hardware. Field Programmable Gate Arrays (FPGAs) are becoming the device of choice for ground based high-performance computing, with tens of millions of gates… More

A significant element of costs and development time for a satellite is the complexity of the avionics (command and control, interface electronics, data storage, etc.). Typically, the approach is to design a unique system for a specific mission incurring high costs and risk associated with… More

SEAKR's ReConfigurable Computers (RCC) offers a flexible reprogrammable platform that is designed to support many spacecraft applications from interface electronics controls, guidance and navigation control, or high end processing of sensor data. The RCC architecture reduces risk, costs, and… More

In their current state, memory density and its associated packaging costs will be a limiting factor in supporting the various Network Centric Warfare (NCW) mission capability packages that tomorrow's aircraft will be asked to perform. Any rugged memory platform, whether it is currently being… More

A lower cost satellite transceiver is of particular importance to the U.S. Government's technology development programs. SEAKR Engineering, Inc. and RT Logic have teamed together to develop a programmable satellite transponder (PST). The PST is a small S-Band/L-Band reprogrammable satellite… More

Demand for high performance On-Board Processing (OBP) for space-based applications is being driven by the advancement of high speed sensors, downlink rates that are orders of magnitudes less than sensor data rates, and the desire for autonomous real-time operations. ReConfigurable Computers (RCC)… More

As the US DOD and other agencies continue to undertake ever-challenging missions, the performance of space On-Board Processing (OBP) is often the limiting factor on what is achievable for a given mission objective. To meet this demand, the defense industry as a whole has increasingly incorporated… More

Today, memory and payload processing systems for space applications are typically designed for a specific application for a specific mission. Many of these systems do not employ a commercial standard which adversely affects the development costs, risks, and schedule while minimizing effective reuse… More

SEAKR Engineering's Application Independent Processor (AIP) standard product integrates FPGAs, GPPs and malleable interface support into a flexible onboard processor designed to support many spacecraft applications. The AIP architecture reduces risk, costs, and schedule for satellite missions by… More

The MAESTRO Phase II SBIR's focus is the design and build of a single board processor based on the MAESTRO chip developed by the U.S. Government. The board will be on a commercial VPX (Vita-46) 6U standard. The processor chip used on the board is a multi-core processor, with 49 identical… More

While VPX shows promise as an open standard COTS computing and memory platform, there are several challenges that must be overcome to migrate the technology for a space application. For the Phase I SBIR, SEAKR investigated the 3u VPX architecture for the space environment for advanced memory and… More

ABSTRACT: High-speed inter-satellite links (ISLs) are a key feature to improving satellite communications (satcom) bandwidth in support of global military operations. ISLs increase the number of paths in the network which tend to improve aggregate bandwidth, network survivability, and improve the… More

ABSTRACT: The need for improved routing to support ad-hoc satellite communications is apparent and protocol research has been performed to date which would greatly impact future DoD systems. The Internet Router in Space (IRIS)technology developed by SEAKR and Cisco has provided an advantageous… More

ABSTRACT: High-speed inter-satellite links (ISLs) are a key feature to improving satellite communications (SATCOM) bandwidth in support of global military operations. ISLs increase the number of paths in the network which tend to improve aggregate bandwidth, network survivability, and improve the… More