Based on our analysis, we believe the biggest technology difficulty will be the pixel layout real estate constraint created by the 20um pixel pitch against the various specification requirements like two color, low flux operation, low noise, high dynamic range, variable gain, integrate while read,… More

The objective of this proposal is to use the proprietary knowledge of Read Out Integrated Circuit (ROIC) unit cell and architecture design from Infrared Laboratories, Inc. (IRL) and Valley Oak Semiconductors, LLC (VOS, a wholly owned subsidiary of IRL), to develop and demonstrate a smart ROIC for… More

The objective of this proposal is to use the proprietary knowledge of readout integrated circuit (ROIC) design gained through our past 20+ years of experience to investigate, research and design a dedicated readout architecture optimized for the high performance C-QWIP PDAs developed by the Army… More

In Phase-I of the project we constructed a unique ROIC design based on our Amplifier-Shared-Dual-Band CTIA (ASDBC) technology to address the problems experienced by the existing ROICs. In Phase-II, we will refine and complete the design, manufacture the ROIC, fabricate the FPA, and test the… More

The SBIR MDA11-005 posted a well depth requirement of up to 50 Million electrons for a pixel pitch of 12um~20um to achieve the targeted high dynamic range, low noise and high resolution imaging goal. Initial calculations, given a commercial 0.18um/3.3V process, and using the entire pixel area at the… More