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SBIR Phase I: TBC - Test Bench Compaction for Improving the Efficiency of…

Award Information

Agency:
National Science Foundation
Branch:
N/A
Award ID:
98873
Program Year/Program:
2010 / SBIR
Agency Tracking Number:
0945452
Solicitation Year:
N/A
Solicitation Topic Code:
3H
Solicitation Number:
N/A
Small Business Information
Envis
4800 Patrick Henry Drive Santa Clara, CA 95054-1820
View profile »
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 1
Fiscal Year: 2010
Title: SBIR Phase I: TBC - Test Bench Compaction for Improving the Efficiency of Full-Chip Power and Thermal Evaluation
Agency: NSF
Contract: 0945452
Award Amount: $126,558.00
 

Abstract:

This Small Business Innovation Research (SBIR) Phase I project will develop a test bench compactor to reduce the length of the test benches used for the power analysis of Very Large Scale Integration (VLSI) designs by up to two orders of magnitude. Accurate estimation of the average and peak power consumptions as well as die temperature of a design usually requires detailed simulations at the gate level. This makes the power estimation step computation intensive and very time consuming. The proposed test bench compactor will take a long register-transfer level (RTL) test bench (which is representative of the typical applications running on a chip or design) and shorten its length to reduce the required simulation time, while preserving the spatio-temporal characteristics of the original test bench which are important for accurate power estimation. The proposed approach will take into account the power modes of the design and the status of its clock and power gaters during the test bench compaction to achieve high accuracy. It will thereby significantly reduce the time required for estimating power consumption of VLSI circuits while maintaining the fidelity of the power estimates. The broader impact and commercial potential of the proposed work will have a direct impact on reducing the effort for designing and validating nano-electronic circuits and semiconductor chips. It will thus significantly reduce the design time and reduces the number of redesigns required to meet the power budget by providing an accurate, yet very fast, estimation of the average and peak power consumption/temperature of the chips. The semiconductor industry and design houses (doing custom designs such as microprocessor and embedded cores as well as application specific designs such as network adapters and various codecs) are expected to greatly benefit from such a capability, and therefore, the commercial potential of this proposed test bench compactor is huge. There are no existing tools in the market that utilize the proposed compaction technology and solution strategy. Finally the proposed SBIR Phase I project will enhance fundamental understanding of effects of the salient characteristics of application data in conjunction with the specific micro-architectural features of target hardware on power modeling and analysis, with wide ranging applications to performance modeling and power-performance tradeoff analysis.

Principal Investigator:

Hamid Savoj
PhD
6502183019
hamid@envis.com

Business Contact:

Hamid Savoj
PhD
6502183019
hamid@envis.com
Small Business Information at Submission:

Envis
4800 Patrick Henry Drive Santa Clara, CA 95054

EIN/Tax ID: 203846391
DUNS: N/A
Number of Employees:
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No