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Array Clocking with Reduced Jitter Using Taped Delay Lines

Award Information

Agency:
Department of Defense
Branch:
Navy
Award ID:
77008
Program Year/Program:
2006 / SBIR
Agency Tracking Number:
N062-164-0886
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
FTL Systems, Inc.
1620 Greenview DR SW Rochester, MN -
View profile »
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 1
Fiscal Year: 2006
Title: Array Clocking with Reduced Jitter Using Taped Delay Lines
Agency / Branch: DOD / NAVY
Contract: N00014-07-M-0062
Award Amount: $69,369.00
 

Abstract:

Deriving coherent antenna array clocks from a common tapped delay line driven by a synchronizing pulse per clock cycle results in reduced jitter and optimal beam forming at minimal cost. Phase one effort analytically considers both electronic and optical implementations with an option for simulation-based validation of a critical PLL circuit and other physical parameters. Analysis considers three clock configurations: 1Ghz with 100FS aperature jitter (per RFP), 21Ghz (2 times X-band) with 50FS jitter and 40GHz (2 times low end of K-band) with 10FS jitter.

Principal Investigator:

John Willis
CEO
5072883154
jwillis@ftlsystems.com

Business Contact:

Ruth Betcher
CFO
5072883154
ruth.betcher@ftlsystems.com
Small Business Information at Submission:

FTL SYSTEMS, INC.
1620 Greenview DR SW Rochester, MN 55902

EIN/Tax ID: 411818690
DUNS: N/A
Number of Employees:
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No