High-speed Digital Filters for Multi-Band Digital-RF Channelizing Receivers
Agency / Branch:
DOD / ARMY
HYPRES proposes to develop an ultrafast third-order digital decimation filter for integration with second-order bandpass delta-sigma analog-to-digital converters (ADCs) that convert radio frequency (RF) signals directly to digital. The proposed filter represents a unique class of RF digital signal processors, which enable the software reconfigurable digital-RF transceiver architecture. The digital-RF transceiver permits the replacement of multiple analog mixers, filters, routers, and amplifiers with lower-noise, less expensive, and programmable digital counterparts. The proposed effort to build a higher order cascaded integrator comb (CIC) filter will allow us to fully exploit the noise-shaping properties of delta-sigma ADCs. We propose to double the complexity of RSFQ digital circuitry, which presents considerable challenge for both integrated circuit design and fabrication and will test the capabilities of our newly upgraded commercial foundry. We will investigate serial biasing of a chain of identical circuit blocks to reduce the total bias current and prevent deleterious effects of induced local magnetic fields. In Phase I, we will design filters in both first and second-generation fabrication processes, corresponding to clock speeds of 20 GHz and 40 GHz respectively. The full implementation and integration with ADC modulators will be performed in Phase II, starting with the Phase I option.
Small Business Information at Submission:
VP, Research and Development
175 Clearbrook Road Elmsford, NY 10523
Number of Employees: