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Low Jitter On-chip Clock Technology
- Small Business Information
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Woman-Owned: NoMinority-Owned: NoHUBZone-Owned: No
- Phase 1
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Fiscal Year: 2006Title: Low Jitter On-chip Clock TechnologyAgency / Branch: DOD / ARMYContract: W15P7T-07-C-E201Award Amount: $69,937.00
Abstract:
In true Digital-RF receiver technology, the RF signal is sampled directly at the antenna and processed digitally at high speeds. This requires an ultrafast ultra-linear analog-to-digital Converter (ADC) followed by ultrafast digital signal processing (DSP). High-speed clocks, in the 20 - 120 GHz range, are required for both the ADC and the DSP. For best performance, the ADC clock must have extremely low short-term jitter, preferably 10 fs (0.01 ps) or less. HYPRES has previously demonstrated that a Long Josephson Junction (LJJ) oscillator may be used as a clock source that meets all of these requirements, and can be integrated with rapid-single-flux-quantum (RSFQ) superconductor digital circuits. HYPRES proposes to develop a parametric family of high-frequency LJJ clocks, and to fabricate and test such an on-chip clock, phase-locked to an external low-frequency reference oscillator for long-term stability. In Phase II, a programmable modular multi-rate clock will be integrated with a superconducting ADC and DSP to provide a complete, compact digital-RF receiver system for Army communications.Small Business Information at Submission:HYPRES., INC.
175 Clearbrook Road Elmsford, NY 10523EIN/Tax ID: 133170343DUNS: N/ANumber of Employees:Woman-Owned: NoMinority-Owned: NoHUBZone-Owned: No
Award Information
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Agency: Department of Defense |
Branch: Army |
Award ID: 77468 |
Program Year/Program: 2006 / SBIR |
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Agency Tracking Number: A062-099-1208 |
Solicitation Year: N/A |
Solicitation Topic Code: N/A |
Solicitation Number: N/A |