Wafer Bumping for Ultra-High Data Transfer Rates in Multi-Chip Modules with Superconducting Integrated Circuits

Superconducting integrated circuits (ICx) have recently demonstrated record breaking performances in direct digitization and channeling of RF signals for military and satellite communications in frequency bands from HF to X-band (8-12 GHz) Superconducting ICs offer unparalleled clock frequency of 30 GHz that very soon is going to be increased above 50 GHz allowing for a direct digitization of signals in the K-band (12-18 GHz), K-band (18-26 GHz), and beyond. Multi-channel all-digital RF receivers and other complex RF systems for the Navy, Army and other DoD components can be built by using mult-chip modules. This requires multiple chips on the module to communicate at full clock rates (>20 GHz) and with low cross-talk. The existing techniques of bumping individual superconducting chips is a slow and low yield manual process based on molten solder dipping. It is proposed to develop and transer to HYPRES a technology of the wafer-scale bumping based on bump evaporation (base) and bump electroplating (option) that would allow for a data transfer rates between superconducting chips in excess of 100 Gb/s with high fidelity and yield. It is also proposed to research and transfer the methods of modeling, experimental evaluation and optimization of high-frequency parameters of bump bonds.