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Design and Fabrication Techniques for 3-Dimensional Integrated Circuits

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: W31P4Q-10-C-0017
Agency Tracking Number: 09SB1-0133
Amount: $99,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: SB091-008
Solicitation Number: 2009.1
Timeline
Solicitation Year: 2009
Award Year: 2009
Award Start Date (Proposal Award Date): 2009-12-21
Award End Date (Contract End Date): 2010-08-23
Small Business Information
5821 Sky Park Dr.
Plano, TX 75093
United States
DUNS: 828058508
HUBZone Owned: No
Woman Owned: Yes
Socially and Economically Disadvantaged: No
Principal Investigator
 Nisha Checka
 Chief Executive Officer/Founder
 (617) 642-0857
 nisha@goofyfootlabs.com
Business Contact
 Nisha Checka
Title: Chief Executive Officer/Founder
Phone: (617) 642-0857
Email: nisha@goofyfootlabs.com
Research Institution
N/A
Abstract

The 3-D integration of systems through monolithic wafer stacking is an emerging technology that can alleviate power, delay, and area problems for digital circuits and can enable a host of new applications in the System-on-Chip design space. Currently, CAD tools for 3-D integration are severely lacking stagnating potentially explosive growth of the technology. GoofyFoot Labs will develop a CAD verification suite to accurately and efficiently simulate 3-D ICs for issues that are of chief concern to 3-D designers: thermal, signal integrity, and reliability. Existing commercial 3-D CAD tools are limited to place and route and layout. No commercial tool exists to perform full-scale verification incorporating 3-D thermal and signal integrity effects. Designers can use the proposed CAD tool at all stages of the design cycle to determine the performance and reliability effects induced by wafer stacking. During Phase I, we will develop the tool framework and algorithms and demonstrate performance improvements achievable with the new framework. During Phase II, we will develop a full-scale prototype, which will then be used to design and evaluate and an ultra low power, 3-D integrated sensor.

* Information listed above is at the time of submission. *

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