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Company Information:

Company Name: Jrs Research Laboratorytori
City: Orange
State: CA
Zip+4: 92665
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
Website URL: N/A
Phone: N/A

Award Totals:

Program/Phase Award Amount ($) Number of Awards
SBIR Phase I $435,807.00 8
SBIR Phase II $814,000.00 2

Award List:

MICROPROGRAMMED PROCESSORS

Award Year / Program / Phase: 1983 / SBIR / Phase I
Agency: NASA
Principal Investigator: Erwin h. warshawsky , PRINCIPAL INVESTIGATOR
Award Amount: $45,000.00
Abstract:
The use of horozontally microprogrammed processors for performance advantages is well known. the advent of tools for the automatic generation and optimization of microcode for these micro-architectures has raised the question of design issues which directly contribute to performance. in paticular,… More

AUTOMATIC DERIVATION OF PERFORMANCE CONSTRAINTS AND GENERATION OF DESIGN GUIDELINES

Award Year / Program / Phase: 1986 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Robert J Sheraga
Award Amount: $49,951.00

AUTOMATIC DERIVATION OF PERFORMANCE CONSTRAINTS AND GENERATION OF DESIGN GUIDELINES

Award Year / Program / Phase: 1987 / SBIR / Phase II
Agency / Branch: DOD / USAF
Principal Investigator: Robert J Sheraga
Award Amount: $340,000.00
Abstract:
One of the major issues that exists in the design process for high performance computers is that of determining, specifically, the reasons why a particular design achieves a particular performance measure for an application problem of interest (e.g., a benchmark). that is, it is of interest to know… More

PC BASED VHDL DESIGN SYSTEM

Award Year / Program / Phase: 1988 / SBIR / Phase I
Agency / Branch: DOD / ARMY
Principal Investigator: Robert J Sheraga
Award Amount: $51,329.00

PC BASED VHDL DESIGN SYSTEM

Award Year / Program / Phase: 1989 / SBIR / Phase II
Agency / Branch: DOD / ARMY
Principal Investigator: Robert J Sheraga
Award Amount: $474,000.00
Abstract:
The anticipated requirement to use vhdl as a language for describing hardware in dod systems will force government contractors to acquire or build software systems to support vhdl processing. the existig software systems run on expensive computer equipment. this proposal is to provide a low cost… More

IC DESIGN HARDWARE/SOFTWARE COMMUNICATIONS PROTOCOLS

Award Year / Program / Phase: 1989 / SBIR / Phase I
Agency / Branch: DOD / NAVY
Principal Investigator: Robert J Sheraga
Award Amount: $49,974.00
Abstract:
One of the most difficult problems facing senior designers and design managers today is that of interfacing between the various tools and systems that have proliferated over the past few years to aid in the process of designing and developing lsi and vlsi chips, including vhsic and asic. the number… More

PROVIDING FULL ADA SUPPORT FOR THE AN/UYS-2

Award Year / Program / Phase: 1991 / SBIR / Phase I
Agency / Branch: DOD / NAVY
Principal Investigator: Robert J Sheraga , Principal Investigator
Award Amount: $49,874.00
Abstract:
The purpose of this effort is to study, design, implement, and program and the attendant benefits in life cycle costs, software reusability, and reliability. the an/uys-2 is a system that embodies the concepts associated with dynamically distributed parallel processing, particularly as applied to… More

AUTOMATICALLY RETARGETABLE ADA AND C COMPILERS FOR MULTI-PROCESSOR NETWORKS

Award Year / Program / Phase: 1993 / SBIR / Phase I
Agency / Branch: DOD / NAVY
Principal Investigator: Robert J. Sheraga
Award Amount: $50,175.00
Abstract:
JRS is proposing to provide a software tool that will demonstrate efficient mapping of Ada and ANSI Standard "C" onto Uni-processor architecture, based on VHDL models of the target architecture. This demonstration will utilize the JRS IDAS tool set, which has been effectively applied to this… More

The Functional Prototyping System

Award Year / Program / Phase: 1994 / SBIR / Phase I
Agency / Branch: DOD / NAVY
Principal Investigator: William R. James
Award Amount: $69,504.00
Abstract:
The purpose of the proposed effort is to study the feasibility of and implement a very high performance simulation and prototyping tool for embedded, application specific processors. A major problem facing designers of highly stylized application specific processors for embedded military… More

A Library Based Integrated Hardware/Software Codesign Environment (P47LBHSC)

Award Year / Program / Phase: 1995 / SBIR / Phase I
Agency / Branch: DOD / ARMY
Principal Investigator: Robert J. Sheraga
Award Amount: $70,000.00
Abstract:
JRS is proposing to provide a complete integrated hardware/software codesign environment that provides visual programming capabilities and reusable, plug-in hardware and software parts libraries. The system is referred to as the MultiProcessor Compilation System (MCS). It is based on the JRS IDAS… More