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VLSI HIGH THROUGHPUT RATE ARCHITECTURES FOR SYSTOLIC ARRAY PROCESSORS

Award Information

Agency:
National Science Foundation
Branch:
N/A
Award ID:
10690
Program Year/Program:
1990 / SBIR
Agency Tracking Number:
10690
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
Linknet
710 Silver Spur Rd #285 Rolling Hills Est, CA 90274
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Woman-Owned: No
Minority-Owned: Yes
HUBZone-Owned: No
 
Phase 2
Fiscal Year: 1990
Title: VLSI HIGH THROUGHPUT RATE ARCHITECTURES FOR SYSTOLIC ARRAY PROCESSORS
Agency: NSF
Contract: N/A
Award Amount: $199,582.00
 

Abstract:

THE LEAST-SQUARES (I.S.) ALGORITHM IS THE BASIS FOR MANY MODERN SIGNAL PROCESSING APPLICATIONS INCLUDING SPECTRAL ANALYSIS, BEAM FORMATION, DIRECTION FINDING, ADAPTIVE ANTENNA ARRAY, EQUALIZATION, KALMAN FILTERING AND PARAMETER ESTIMATION. TRIANGULAR AND LINEAR SYSTOLIC ARRAYS ARE THE MOST EFFICIENT WAYS TO ACHIEVE HIGH COMPUTATIONAL THROUGHPUTRATES FOR HIGH PERFORMANCE REAL-TIME APPLICATIONS. THE RESEARCHERS PROPOSE A DETAILED COMPARISON OF THE ARITHMETICAL COMPLEXITY (NUMBER OF MULTIPLES, DIVIDES, ETC.)AND FINITE PRECISION COMPUTATIONAL EFFECTS OF THE TRIANGULARAND LINEAR INTERNAL AND BOUNDARY SYSTOLIC PROCESSING CELLS UNDER GIVENS, FAST GIVENS, MODIFIED FAST GIVENS, MODIFIED GRAM-SCHMIDT, AND HOUSEHOLDER TRANSFORMATIONS FOR I.S. ESTIMATION BASED ON THE QR DECOMPOSITION APPROACH. BY SELECTING THE PROCESSING ALGORITHM WITH THE LEAST COMPUTATIONAL COMPLEXITY, THEY CAN DETERMINE THE ARCHITECTURE OF THE HIGH THROUGHPUT RATE SYSTOLIC ARRAY PROCESSOR FOR VLSI FABRICATION. A GENERIC (PROGRAMMABLE) SYSTOLIC ARRAY PROCESSING CHIP CAN BE DEVELOPED FOR A VARIETY OF SIGNAL PROCESSING APPLICATIONS.

Principal Investigator:

Tsun-yee Yan
Principal Investigator
2133733384

Business Contact:

Small Business Information at Submission:

Linknet
710 Silver Spur Rd #285 Rolling Hills Est, CA 90274

EIN/Tax ID:
DUNS: N/A
Number of Employees: N/A
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No