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Company Information:

Company Name: MICROELECTRONICS RESEARCH DEVELOPMENT CORP.
City: Colorado Springs
State: CO
Zip+4: -
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
Phone: (719) 531-0805

Award Totals:

Program/Phase Award Amount ($) Number of Awards
SBIR Phase I $1,799,248.00 18
SBIR Phase II $22,914,550.00 9
STTR Phase I $99,994.00 1
STTR Phase II $999,998.00 1

Award List:

Advanced Encryption Techniques for the Prevention of Reverse Engineering of the Programming Code in Military and Space Custom ICs and FPGAs

Award Year / Program / Phase: 2006 / STTR / Phase I
Agency / Branch: DOD / MDA
Research Institution: ARIZONA STATE UNIV.
Principal Investigator: Paul H. Eaton, Chief Engineer
Award Amount: $99,994.00
RI Contact: Lawrence Clark
Abstract:
We propose the development of advanced encryption techniques to make integrated circuits more secure against unauthorized intrusion, specifically the use of innovative embedded techniques to make reprogramming of high performance deep sub-micron or nano-scale FPGA or custom ASIC systems by other… More

Radiation Hardened By Design Structure ASICs for Reliable Digital Components

Award Year / Program / Phase: 2006 / SBIR / Phase I
Agency / Branch: DOD / MDA
Principal Investigator: Dave Mavis, Senior Engineer – (505) 507-0542
Award Amount: $99,999.00
Abstract:
Recent advances in radiation hardening by design (RHBD) techniques for deep sub-micron semiconductor technologies enable fabrication of rad hard microcircuits through commercial foundries. By applying these techniques to an emerging single-mask, via-prog

Dual Chip Approach to Radiation Hardened Logic

Award Year / Program / Phase: 2006 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: David Mavis, Senior Design Engineer
Award Amount: $99,977.00
Abstract:
We wish to offer users nearly ASIC density (20X higher logic density than FPGAs), yet allow them to develop their systems with off-the-shelf FPGA-based parts. The core idea is to use a new high-density non-rad-hard FPGA for development, and an electrically and timing equivalent, rad-hard by design… More

Hardened by Design Cryogenic Infrared Focal Plane Array Readout Integrated Circuit

Award Year / Program / Phase: 2007 / SBIR / Phase I
Agency / Branch: DOD / MDA
Principal Investigator: Joseph Benedetto, Principal Investigator
Award Amount: $100,000.00
Abstract:
We have developed transistor level radiation tolerant design techniques for the manufacture of radiation resistant digital and mixed signal devices, including infrared (IR) focal plane array (FPA) readout integrated circuits (ROICs), and verified the operation and radiation performance to 43K (-230… More

Ultra-Fast Level 2 Cache SRAM for High-Performance Military and Spaceborne Computing

Award Year / Program / Phase: 2007 / SBIR / Phase I
Agency / Branch: DOD / MDA
Principal Investigator: Joseph M. Benedetto, Principal Investigator
Award Amount: $100,000.00
Abstract:
In this proposal we discuss the development of an ultra high-speed synchronous SRAM suitable for use as an embedded level 1 or external level-2 cache memory. The state-of-the-art radiation tolerant/hardened memory devices are of an asynchronous design with access times of 17 to 30ns. The… More

Enhanced Security Features for Commodity Integrated Circuits

Award Year / Program / Phase: 2007 / SBIR / Phase I
Agency / Branch: DOD / MDA
Principal Investigator: Martin Denham, Principal Investigator
Award Amount: $100,000.00
Abstract:
COTS IC manufacturing technologies are capable of deployment to spaced-based vehicles. Their performance levels, degree of innate rad-hardness, and cost-effective yields make them compelling for U.S. strategic launch vehicles. It is of concern that some of the 'generation-N' COTS IC fabrication… More

Radiation Hardened By Design Structured ASICs for Reliable Digital Components

Award Year / Program / Phase: 2007 / SBIR / Phase II
Agency / Branch: DOD / USAF
Principal Investigator: David G. Mavis, Chief Scientist
Award Amount: $6,108,306.00
Abstract:
The Phase II effort will fully develop and realize a cost-effective, practically-oriented means to design and deliver radiation hardened digital electronic components capable of reliable operation in MDA and other DoD space and interceptor environments. Micro-RDC will accomplish this by working… More

Dual Chip Approach to Radiation Hardened Logic

Award Year / Program / Phase: 2007 / SBIR / Phase II
Agency / Branch: DOD / USAF
Principal Investigator: Patrick McGuirk, Principal Investigator
Award Amount: $1,490,524.00
Abstract:
In an electronics system, the incorporation of reprogrammable logic, such as Field Programmable Gate Arrays (FPGAs), into the design can offer many benefits to a digital designer. For radiation hardened reprogrammable electronics, the choices among appropriate devices are very limited. AFRL is at… More

Advanced IC Design Techniques for the Prevention of Reverse Engineering of the Programmed Functionality in FPGAs

Award Year / Program / Phase: 2007 / STTR / Phase II
Agency / Branch: DOD / MDA
Research Institution: ARIZONA STATE UNIV.
Principal Investigator: Martin S. Denham, Principal Investigator
Award Amount: $999,998.00
RI Contact: Larry Clark
Abstract:
Military and space-application FPGAs are invaluable for improving defense capabilities and deployment schedules; however, they also create a potential vulnerability if their configuration code can be discerned or if they can be directly used in unauthorized systems. Modern IC debug and repair… More

SEE Modeling and Mitigation in Ultra-Deep Submicron Microelectronics

Award Year / Program / Phase: 2007 / SBIR / Phase I
Agency / Branch: DOD / DTRA
Principal Investigator: David G. Mavis, Chief Scientist
Award Amount: $100,000.00
Abstract:
As technology feature sizes decrease, single event upset (SEU), digital single event transient (DSET), and multiple bit upset (MBU) effects dominate the radiation response of microcircuits. Recent test circuits and test methods have quantified the pulse widths of DSETs generated from heavy-ion… More

Radiation Hardened By Design Structured ASICs for Reliable Digital Components

Award Year / Program / Phase: 2007 / SBIR / Phase II
Agency: DOD
Principal Investigator: David G. Mavis, Chief Scientist – (505) 507-0542
Award Amount: $9,576,239.00
Abstract:
The Phase II effort will fully develop and realize a cost-effective, practically-oriented means to design and deliver radiation hardened digital electronic components capable of reliable operation in MDA and other DoD space and interceptor environments. Micro-RDC will accomplish this by working… More

Novel Mitigation Techniques for Reconfigurable Computers for Space Based Applications

Award Year / Program / Phase: 2008 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Keith Avery, Principle Investigator
Award Amount: $99,946.00
Abstract:
Reconfigurable systems popularity for space-based applications has grown considerably due to their flexibility and the ability to multiplex in real time different hardware configurations based on the demand of the system application. Commercial FPGA based designs are susceptible to Single Event… More

Design-Hardened Radiation Tolerant Microelectronics

Award Year / Program / Phase: 2008 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Michael Sibley, Principal Investigator
Award Amount: $99,974.00
Abstract:
Producing components that satisfy all of the BMDS space and interceptor environment specs traditionally has been not only costly but also untimely. One of the most difficult design constraints is making the components unaffected by the radiation environments of space. We propose to develop and… More

Space Qualified SDRAM Memory

Award Year / Program / Phase: 2008 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Dean Allum, Principal Investigator
Award Amount: $99,969.00
Abstract:
The Phase 1 effort is aimed at finding the specific physical defects which prevent a Commercial SDRAM at the 512 Megabit density from being Space Qualified. The goal is to find the exact failure locations of Radiation "Soft" circuits. Scanning Laser Microscopy will locate latch-up sites. Heavy Ion… More

SEE Modeling and Mitigation in Ultra-Deep Submicron Microelectronics

Award Year / Program / Phase: 2008 / SBIR / Phase II
Agency / Branch: DOD / DTRA
Principal Investigator: David Mavis, Chief Scientist
Award Amount: $749,948.00
Abstract:
OBJECTIVE: The objectives of this task are to: 1. Characterization of Single-Event Effects in ultra-deep submicron (< 90nm) integrated circuits and 2. Development and demonstration of minimally invasive methods to mitigate SEE in ultra-deep submicron digital and analog/mixed-signal integrated… More

Reliable and Rad-Hard Microelectronics

Award Year / Program / Phase: 2009 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Michael Sibley, Senior Research Scientist
Award Amount: $99,917.00
Abstract:
Producing components that satisfy all of the BMDS space and interceptor environment specs traditionally has been not only costly but also untimely. As semiconductor companies continue along path set by Moores Law producing chips that have the necessary lifetime of a MIL Space application is a matter… More

Exploiting Commercial Microelectronics for Space Applications

Award Year / Program / Phase: 2009 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Steve Dilllinger, Vice-President
Award Amount: $99,934.00
Abstract:
State-of-the-art integrated circuit serializer/deserializers (SERDES) produced at 90nm geometries and below have identified Single Event Effect (SEE) hardness weaknesses, especially Single Event Transient (SET) induced multiple bit data loss in high speed data paths. MRDC will address these effects… More

Multi-Cluster Network on a Chip Reconfigurable Radiation Hardened Radio

Award Year / Program / Phase: 2009 / SBIR / Phase I
Agency: NASA
Principal Investigator: Sasan Ardalan, Principal Investigator
Award Amount: $99,968.00
Abstract:
The objective of the Phase-I research is to architect, model and simulate a multi-cluster Network on a Chip (NoC) reconfigurable Radio in SystemC RTL, with throughput up to 1Gbps. The architecture is based on mapping key Radio DSP operations onto clusters of 2D-Grid networks of primitive… More

Design-Hardened Radiation Tolerant Microelectronics

Award Year / Program / Phase: 2009 / SBIR / Phase II
Agency: DOD
Principal Investigator: Michael Sibley, Engineer II – (505) 294-1962
Award Amount: $1,249,994.00
Abstract:
Producing components that satisfy all of the BMDS space and interceptor environment specs traditionally has been not only costly but also untimely. One of the most difficult design constraints is making the components unaffected by the radiation environments of space. We propose to develop and… More

Novel Mitigation Techniques for Reconfigurable Computers for Space Based Applications

Award Year / Program / Phase: 2009 / SBIR / Phase II
Agency / Branch: DOD / USAF
Principal Investigator: Alonzo Vera, Engineer
Award Amount: $741,348.00
Abstract:
FPGA-based reconfigurable systems'''' popularity for space-based applications has grown considerably due to their flexibility and the ability to multiplex in real time different hardware configurations. A wider utilization of COTS FPGAs is limited by their susceptibility to Single Event Upsets… More

Deep Submicron Radiation Hardened Logic for Communications

Award Year / Program / Phase: 2009 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Stephen Philpy, President
Award Amount: $99,930.00
Abstract:
Micro-RDC will investigate scaling our 90nm Design-Hardened Structured ASIC (DH SASIC) to deep submicron (65nm, with considerations towards 45nm) feature sizes, enabling the design and fabrication of high-performance digital integrated circuits for satellite communications systems, especially for… More

Radiation-Hardened Memory

Award Year / Program / Phase: 2009 / SBIR / Phase I
Agency / Branch: DOD / MDA
Principal Investigator: Dean Allum, Principal Investigator
Award Amount: $99,967.00
Abstract:
Micro-RDC will develop a Radiation Hardened 16Mbit SONOS based EEPROM with the highest levels of reliability. It will be manufactured in 180nm technology at a high volume, high yielding semiconductor foundry. The product will include techniques such as redundancy, internal EDAC, hardened latches… More

Low Power, Radiation Hardened Embedded Memory Compiler

Award Year / Program / Phase: 2010 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: John Bailey, Sr Design Engineer
Award Amount: $99,968.00
Abstract:
Micro-RDC will develop a low power, radiation hardened memory compiler suitable for use in current and future satellite missions. The memory compiler will generate embedded memory blocks hardened against Total Ionizing Dose effects, Single Event Upsets, Single Event Latch-up, and Single Event… More

Radiation-Hardened Memory

Award Year / Program / Phase: 2010 / SBIR / Phase II
Agency / Branch: DOD / MDA
Principal Investigator: Dean Allum, Sr. Design Engineer
Award Amount: $1,499,722.00
Abstract:
Micro-RDC is developing a Radiation Hardened 64Mbit SONOS based Nonvolatile Memory with the highest levels of reliability. It will be manufactured in a130nm technology at a high volume, high yielding semiconductor foundry. No process development will be needed for this project. The product will… More

Deep Submicron Radiation Hardened Logic for Communications

Award Year / Program / Phase: 2010 / SBIR / Phase II
Agency / Branch: DOD / USAF
Principal Investigator: Steve Philpy, Director of Programs
Award Amount: $748,508.00
Abstract:
The development of advanced microelectronics for satellite communications applications have become increasingly expensive. Smaller feature-sized microelectronics fabrication is now needed to provide ICs for complex radiation-hardened communications systems operating in space. Historically,… More

High Performance Ultra Low-Power ADCs and DACs

Award Year / Program / Phase: 2011 / SBIR / Phase I
Agency: NASA
Principal Investigator: Sasan Ardalan, Principal Investigator
Award Amount: $99,964.00
Abstract:
The objective of the Phase-I research is to design a multi-GHz high bandwidth Delta Sigma Analog-to-Digital and Digital-to-Analog converter using a deep sub-micron CMOS process. Since the Delta Sigma Modulation ADC samples in the multi-GHz range, direct sampling and conversion to digital of post LNA… More

Technologies Enabling Custom Radiation-Hardened Component Development

Award Year / Program / Phase: 2011 / SBIR / Phase I
Agency: NASA
Principal Investigator: Xiaoyin (Mark) Yao, Principal Investigator
Award Amount: $99,991.00
Abstract:
Two primary paths are available for the creation of a Rad-Hard ASIC. The first approach is to use a radiation hardened process such as existing Rad-Hard foundries. These foundries use special processing steps to decrease the total ionizing dose issues, but do not reduce the single event effects. … More

Strategically Radiation-Hardened Star Tracker

Award Year / Program / Phase: 2011 / SBIR / Phase I
Agency: DOD
Principal Investigator: Xiaoyin (. Yao, Engineer – (505) 294-1962
Award Amount: $99,744.00
Abstract:
ABSTRACT: We propose a new radiation-hardened star tracker system which will provide high-precision performance while meeting all radiation requirements listed in the solicitation. It has a baffle, focal-plane arrays, microprocessor, memory and power supply. The key component is a high-performance… More

Low Power, Radiation Hardened Embedded Memory Compiler

Award Year / Program / Phase: 2011 / SBIR / Phase II
Agency: DOD
Principal Investigator: Dean Allum, Design Engineer – (719) 531-0805
Award Amount: $749,961.00
Abstract:
ABSTRACT: Micro-RDC will develop a low power, radiation hardened memory compilers suitable for use in current and future satellite missions. The memory compilers can quickly generate embedded memory blocks hardened against Total Ionizing Dose effects, Single Event Upsets, Single Event Latch-up,… More