You are here

DEVELOPMENT OF 32 BIT SINGLE BOARD COMPUTER SYSTEMS IN FASTBUS PACKAGING

Award Information
Agency: Department of Energy
Branch: N/A
Contract: N/A
Agency Tracking Number: 422
Amount: $499,992.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1984
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
106 Rocky Point Gardens
Rocky Point, NY 11778
United States
DUNS: N/A
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Eric J. Siskind Ph.d.
 () -
Business Contact
Phone: () -
Research Institution
N/A
Abstract

A FASTBUS PACKAGED 32 BIT COMPUTING SYSTEM INCLUDING BOTH FASTBUS HARDWARE AND SOFTWARE FOR PROGRAM DEVELOPMENT, DEBUGGING, AND RUN-TIME SUPPORT WILL BE DEVELOPED. THE HARDWARE WILL FEATURE A 32 BIT CPU, PREFERABLY IMPLEMENTING THE DEC VAX ARCHITECTURE, BUT NOT IMMEDIATELY EXCLUDING CURRENT OFFERINGS FROM INTEL, MOTOROLA, HEWLETT-PACKARD, OR NATIONAL SEMICONDUCTOR, PLUS ON-CARD MAIN MEMORY IN THE RANGE FROM .5 TO 2.0 MEGABYTES, AND NECESSARY PERIPHERALS INCLUDING A FASTBUS INTERFACE. SOFTWARE WILL INCLUDE CODE DEVELOPMENT AND DEBUGGING TOOLS DESIGNED TO RUN ON A DEC VAXHOST, PLUS DOWNLINE LOADERS AND RUN-TIME SUPPORT DESIGNED TOALLOW COMMUNICATION BETWEEN THE TARGET PROCESSOR AND BOTH THE HOST AND OTHER TARGET PROCESSORS.

* Information listed above is at the time of submission. *

US Flag An Official Website of the United States Government