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INTELLIGENT BUFFER FOR ON-LINE REAL-TIME COMPENSATION OF ARRAY DISTORTIONS

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N/A
Agency Tracking Number: 6202
Amount: $53,645.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1987
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
145 Palisade St
Dobbs Ferry, NY 10522
United States
DUNS: N/A
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 ROSS E WILLIAMS
 (914) 693-9001
Business Contact
Phone: () -
Research Institution
N/A
Abstract

A DESIGN APPROACH USING HIGH SPEED MICROPROCESSORS AND RAPID-ACCESS MEMORY DEVICES IS SUGGESTED FOR A STAND-ALONE INTELLIGENT BUFFER THAT INSERTS DELAYS TO COMPENSATE FOR SENSOR POSITION ERRORS IN THE SENSOR DATA STREAM THAT FEEDS A CONVENTIONAL BEAMFORMER IN REAL-TIME. THE MOTOROLA 68020 AND INTEL 80386 32 BIT HIGH SPEED MICROPROCESSOR CHIPS HAVE SEVERAL ATTRACTIVE FEATURES FOR THIS APPLICATION WHEN USED TO CONTROL THE INSERTION AND REMOVAL OF SERIAL SENSOR DATA IN FIFO FASHION FROM VERY FAST RANDOM OR SERIAL ACCESS MEMORY CHIPS. A BLOCK DIAGRAM IS GIVEN FOR THE SYSTEM CONCEPT. A HYPOTHETICAL ARRAY EXAMPLE IS PRESENTED TO ILLUSTRATE DATA RATES, PROCESSING LOAD, AND REAL-TIME CAPABILITY. IN PHASE I, OAS WILL DETERMINE MAXIMUM DELAYS REQUIRED FOR COMPENSATION AND THE NUMBER OF ANGULAR SECTIONS TO BE COMPENSATED. HARDWARE DESIGN ALTERNATIVES WILL BE EVALUATED AND OPTIMUM COMPONENTS SPECIFIED. A TIMING SEQUENCE WILL BE ESTABLISHED FOR ON-LINE OPERATIONS, AND A FLOW DIAGRAM FOR MICROPROCESSOR SOFTWARE WILL BE DEFINED.

* Information listed above is at the time of submission. *

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