Design Tools for Integrated Asynchronous Electronic Circuits

"Asynchronous circuit design has the potential to offer orders of magnitude improvement in speed, power dissipation and EMI over synchronous circuit design. It is especially appealing to military electronics due to its extremely low EMI performance and itssuitability as an enabling technology for heterogeneous system integration with high reliability and affordability. However, its real silicon success has been extremely limited due to lack of supporting CAD tools. In this SBIR project, we propose todevelop CASTER (CMOS Asynchronous System Timing, Energy and Radiation): a CAD tool for silicon-accurate analysis and optimization of timing, power and EMI of asynchronous circuits. CASTER partitions a transistor-level asynchronous circuit into a graph oftransistor-channel-connected blocks (TCCB) communicating through asynchronous handshaking signals. Each TCCB can be modeled in the same way as in a synchronous CMOS circuit, and can be analyzed by using parasitic-aware behavioral modeling from DARPANeoCAD. We propose to study the feasibility of using CASTER for asynchronous performance metric study and design methodology evaluation. Further, we propose to demonstrate coupled optimization of asynchronous circuit density, speed, power and EMI noise byusing CASTER to incorporate physical design and layout parameters, and then use our ARSYN optimizer for architecture exploration. The proposed CAD tools CASTER/ARSYN can reduce the design cycle t