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GALLIUM ARSENIDE MEMORY APPLICATION STUDY Q-DOT RESEARCH

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: N/A
Agency Tracking Number: 1030
Amount: $500,000.00
Phase: Phase II
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 1985
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
1069 Elkton Drive
Colorado Springs, CO 80907
United States
DUNS: N/A
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Dr. Peter C. T. Roberts
 (303) 590-1112
Business Contact
Phone: () -
Research Institution
N/A
Abstract

TO SUCCESSFULLY EMPLOY THE INTRINSICALLY SHORT ACCESS TIME (I.E., LESS THAN 1NS) OF GAAS DIGITAL MEMORY CHIPS, UNIQUE SIGNAL PROCESSING ARCHITECTURES WILL BE REQUIRED WHICH MAY INFLUENCE CONVENTIONAL FUNCTION PARTITIONING AMONG INTEGRATED CIRCUITS. TO DETERMINE THE OPTIMAL ARCHITECTURE OF BOTH PROCESSOR AND IC'S, A CANDIDATE PROCESSOR OF IMPORTANCE TO THE AIR FORCE WILLL BE SELECTED. ITS ARCHITECTURE WILL BE ANALYZED TO UNCOVER OPPORTUNITIES FOR IMPROVEMENT. THE ARCHITECTURE WILL BE OPTIMIZED FOR GAAS MEMORY. RESULTING STRUCTURES WILLL BE SIMULATED AT BOTH THE CIRCUIT AND SYSTEM LEVELS. BENEFITS OF INTEGRATED LOGIC-MEMORY WILL BE COMPARED TO CONVENTIONAL IMPLEMENTATIONS. A COMPREHENSIVE FINAL REPORT WILL DOCUMENT THE RESULTS.

* Information listed above is at the time of submission. *

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