Breach Capacitor ESD Event Detector (Q-DOT Research Proposal 39-1487)

This proposal presents an electrostatic discharge (ESD) detector which can be integrated on a semiconductor chip. A circuit terminal overvoltage condition is sensed with a passive, nonvolatile write-once memory which can be read out after the ESD event has occurred. The approach provides independent ESD detection on all terminals of the IC in both powered and unpowered states. The ESD status of any terminal can be scanned at any time by powering Vdd and applying a dc voltage to the desired terminal while monitoring the voltage on a common readout terminal. The detector chip area is small, and the detector adds only one additional bond pad to the IC. The detector enables screening of potential ESD damage occurring at the chip, PC board, or equipment level.