Agency / Branch:
DOD / DARPA
The coming generations of multicore systems will provide multiple heterogeneous distributed processors with SIMD capabilities. Effective programming tools must address this variety and the fast rate of architecture evolution of such systems, as well as the variety of parallel applications. An existing parallel programming, PARLANSE, presently proven for fine-grain task parallism on SMP systems, will be extended to include additional parallelism paradigms: nested data parallelism and pipelined streaming operations. Semantic Designs (SD) will define an architectural description language to describe specific multicore systems, including multiple instruction sets, memory hierarchies, performance, and communication primitives. SD will build a PARLANSE compiler ecosystem driven from the architecture description. Whole program analysis and optimization will be used to maximize performance; this in turn will require parallel computation on scale to make it practical. A unique internal data flow representation graph will be used to represent whole source programs, enabling optimization and program partitioning across processors. SD will use its DMS system (already implemented in PARLANSE) to implement the tool set, thereby minimizing risk and providing access to large-scale parallelism needed to support the multicore compiler.
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