The major problem with using machine-independent microprogramming language is effective machine targeting. a microcode compiler is desirable which easily directs the code generator of a high-level language translator is distinct microprogrammable machines. it is proposed to study the partitioing of… More

A study is proposed for compilers to generate code for array/vector processors (such as mpp, cray/ star/ hep) without explicit coding of concurrent operations. a major thrust is the incorporation of ai techniques for the tree-search optimizations to host data flow and functional programming… More

An adaptive algorithm study for array signal processors is sought. the basic approach is to study the hardware/software tradeoffs of conventional (von neumann) and non-von (parallel, pipeline, vector, array, and custom processors) with nonconventional arithmetic (sbnr) in an attempt to identify… More

A study of the efficiencies and engineering trade-offs integrating redundant number system with systolic array processing elements in order to capture the inherent fault tolerant properties of signed digits is proposed. using signed digits reduces carry/borrow distance to a minimum thus realizing… More

Exploratory research is proposed to determine the implementation factors parameters for a new vlsi cell invoking redundant number arithmetic instead of 1's/2's complement. a narrow application towards signal processing (multiply/accumulate intensive) shall drive minimal area and speed designs.… More

Any very high level language (vhll) for strategic defense requires a compiler. new meta compilers using advanced artificial intelligence methods are being studied so that eventual vhll application software can be effectively ported to the several ground-based/satellite-based machines. to do so… More

Signal processing algorithms are multiply/accumulate intensive. novel methods using advanced ic devices are needed. radar digital signal processing and spread spectrum processing task include fft, lms, l, convolution, and spectrum analysis. as examples, 32 x 32 multiplier, 64 x 64 multiplier,… More

Air force missions require computers of immense sustained cpu/io bandwidths, not currently available. these new architectures invoke greater demands on the compilation phase, but current compilers lack the capabilities to generate "parallel" code without considerable human effort. a meta-compiler is… More

In any radar employing an array receiving antenna, signals from a number of antenna elements are appropriately weighted and combined to form various antenna beam outputs. digitam beamforming (dbf) denotes the formation of these beam outputs by digital computer. the elemental signals are sampled and… More

The project involves development of a fast, novel, scientific workstation for solving aeropropulsion system structures with cyclic symmetry exhibiting nonlinear response in high temperatures. an engineering study will map efficient algorithms onto new parallel architecture that is extensible across… More