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MICROELECTRONIC INFORMATION PROCESSING SYSTEMS.

Award Information

Agency:
National Science Foundation 		Branch:
N/A 		Award ID:
7586 		Program Year/Program:
1988 / SBIR
Agency Tracking Number:
7586 		Solicitation Year:
N/A 		Solicitation Topic Code:
N/A 		Solicitation Number:
N/A
Small Business Information
Space Tech Corp
125 Crestridge Dr Fort Collins, CO 80525
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Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 1
Fiscal Year: 1988
Title: MICROELECTRONIC INFORMATION PROCESSING SYSTEMS.
Agency: NSF
Contract: N/A
Award Amount: $49,000.00
 

Abstract:

EXPLORATORY RESEARCH IS PROPOSED TO DETERMINE THE IMPLEMENTATION FACTORS PARAMETERS FOR A NEW VLSI CELL INVOKING REDUNDANT NUMBER ARITHMETIC INSTEAD OF 1'S/2'S COMPLEMENT. A NARROW APPLICATION TOWARDS SIGNAL PROCESSING (MULTIPLY/ACCUMULATE INTENSIVE) SHALL DRIVE MINIMAL AREA AND SPEED DESIGNS. CARRY/BORROW FREE DESIGNS MAY GREATLY ENHANCE MODULAR FAULT-TOLERANT IMPLEMENTATIONS. FOR FURTHER FOCUS, THE EFFICIENT SIGNED BINARY NUMBER REPRESENTATION (SBNR) AS A TRIT-VALUED SUBSET OF GENERAL REDUNDANT NUMBER REPRESENTATIONS AFFORDS MORE IMPROVED AREA/SPEED FOM'S, THUS MAKING SUCH CELLS HIGHLY VLSI-REGULAR. THIS APPLICATION SPECIFIC STUDY SHALL IDENTIFY CRITICAL DESIGN PARAMETERS (MINIMAL LINE WIDTHS, FUNCTIONAL PARTITIONING, VIA'S # OF GATES, INTER/INTRACELL CONNECTIONS) TO AID THE DESIGN ENGINEER. FOCUS IS ON LOWER LEVELS OF COMPUTER ARCHITECTURE COUPLED TO TECHNOLOGY/IMPLEMENTATION ISSUES WHERE SIGNIFICANT DISCOVERIES MAY BE LEVERAGED INTO PRACTICAL SYSTOLIC ARRAYS EXCEEDING THE DESIGN PERFORMANCE OF GAPP AND DAP DEVICES WHILE ACHIEVING BREAKTHROUGHS IN MINIMAL CELL LAYOUTS.

Principal Investigator:

Dr michandrews
0

Business Contact:

Small Business Information at Submission:

Space Tech Corpon
2324 Manchester Court Fort Collins, CO 80526

EIN/Tax ID:
DUNS: N/A
Number of Employees: N/A
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No