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GAAS RISC ARRAY PROCESSOR

Award Information

Agency:
National Aeronautics and Space Administration
Branch:
N/A
Award ID:
8191
Program Year/Program:
1989 / SBIR
Agency Tracking Number:
8191
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
Systems & Processes Engineering Corporat
6800 Burleson Road Building 320 Austin, TX -
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Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 2
Fiscal Year: 1989
Title: GAAS RISC ARRAY PROCESSOR
Agency: NASA
Contract: N/A
Award Amount: $497,972.00
 

Abstract:

SYSTEMS & PROCESSES ENGINEERING CORPORATION (SPEC) HAS DEVELOPED AN INNOVATIVE ARRAY PROCESSOR ARCHITECTURE FOR COMPU- TING FOURIER TRANSFORMS AND OTHER COMMONLY USED SIGNAL PROCESSING ALGORITHMS. THIS ARCHITECTURE IS DESIGNED TO EX-TRACT THE HIGHEST POSSIBLE ARRAY PERFORMANCE FROM STATE-OF- THE-ART GAAS TECHNOLOGY. THE ARCHITECTURAL DESIGN FEATURES A HIGH PERFORMANCE RISC PROCESSOR IMPLEMENTED IN GAAS, ALONGALONG WITH A FLOATING POINT COPROCESSOR AND A UNIQUE ARRAY COMMUNICATIONS COPROCESSOR, ALSO IMPLEMENTED IN GAAS. THE ARCHITECTURE INCLUDES VERY HIGH SPEED, LOW GATE COUNT BIT-SERIAL ARITHMETIC AND COMMUNICATION UNITS IN THE FLOAT- ING POINT AND COMMUNICATION COPROCESSORS, RESPECTIVELY. UTILIZING THE VERY HIGH SPEED OF GAAS, CURRENTLY WITH CLOCK RATES IN EXCESS OF 1 GHZ, BIT-SERIAL UNITS CAN BE USEDTO FORM THE CORE OF COMPLEX ARITHMETIC AND COMMUNICATIONS UNITS. A BIT-SERIAL VLSI ARCHITECTURE IS, IN FACT, IDEAL FORIMPLEMENTATION OF THE COMMUNICATION LINKS BETWEEN PROCESSORSTHE OBJECTIVE OF THE PHASE II PROGRAM IS TO DESIGN AND SIMU-LATE AN ARRAY PROCESSOR UTILIZING HIGH PERFORMANCE GAAS RISCPROCESSORS AND COPROCESSORS.

Principal Investigator:

Dr Gary B Mcmillian
0

Business Contact:

Small Business Information at Submission:

Systems & Processes Engineerin
1406 Smith Road Suite A Austin, TX 78721

EIN/Tax ID:
DUNS: N/A
Number of Employees: N/A
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No