Parallel Algorithms and Infrastructure for Information Technology

SYSTRAN proposes to develop an innovative product to address the need for parallel routines and infrastructures for sorting and graph theoretic algorithms. Phase I proposal describes the development of a novel "portable, adaptive, parallel, sorting algorithm selector system." In Phase I we will examine the feasibility of designing this system and demonstrate its performance. In Phase II, we will extend these ideas to include graph theoretic algorithms, and build a prototype product, which will be softare written in C. In Phase II, we will also examine the feasibility of embedding this innovative system along with the algorithms in ASIC hardware accelerator card(s). These card(s) may also contain additional memory and logic to improve performance. In Phase III, we will market these software/hardware products.

The proposed product will be portable across a number of hardware platforms, including homogeneous and heterogeneous collections of workstations, and scalable parrallel machines such as the Cray T3D and IBM SP-2. The system will include a number of efficient local (single-processor) sorting routines such as radix sort, quicksort and mergesort. It will adapt to the sorting context, and automatically or semi-automatically select the best sorting algorithm(s) for each specific context.