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Parallel Subsampling Frequency Interleaved (PSFI) Bandpass Delta Sigma ADC

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: F33615-02-M-1226
Agency Tracking Number: 021SN-1439
Amount: $99,995.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: N/A
Solicitation Number: N/A
Timeline
Solicitation Year: N/A
Award Year: 2002
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
4027 Colonel Glenn Highway, Suite 210
Dayton, OH 45431
United States
DUNS: 023956415
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Todd Grimes
 Principal Investigator
 (937) 429-9008
 tgrimes@systranfederal.com
Business Contact
 Kenneth Baker
Title: President & COO
Phone: (937) 429-9008
Email: kbaker@systranfederal.com
Research Institution
N/A
Abstract

"As jamming-to-signal ratios increase, an alternative to today's ADC architectures is required for systems, such as the global positioning system (GPS). Current specifications mandate a 50MHz bandwidth, 100 MSPS, 16-bits of resolution, signal-to-noiseratio of 90dB, and a power draw of 100mW. Systran Federal Corporation and Wright State University propose a new ADC architecture that extends the Parallel Time Interleaved Multi-bit Feedback ADC architecture developed under Air Force contractsF33615-01-C-1860 and F33615-00-C-1638, as the basis for a subsampling ADC. The new architecture is called Parallel Subsampling Frequency Interleaved (PSFI) ¿O Bandpass ADC.The PSFI architecture incorporates subsampling theory that allows an ADC to operate at much higher frequencies then normal, lessening the need for Intermediate Frequency stages. Essentially, the carrier frequency is removed, leaving behind only theinformation band. Therefore, adequate bandwidths at high frequencies suitable for use with a GPS in jamming environment are possible.In Phase I we will investigate techniques to develop an optimal, high performance, low power subsamplingADC architecture. Schematic level designs and simulations of the configuration will be implemented together with a fabricated prototype device in Phase II. Devices resulting from the Phase III would find uses in communications, data I/O, and militarymarkets. Our envisioned subsampling PTIMF ADC woul

* Information listed above is at the time of submission. *

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