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Company Information:

Company Name:
Tezzaron Semiconductor Corp.
Address:
1415 Bond St.
#111
Naperville, IL 60563-
Phone:
(630) 505-0404
URL:
EIN:
841512428
DUNS:
844118195
Number of Employees:
165
Woman-Owned?:
No
Minority-Owned?:
No
HUBZone-Owned?:
No

Commercialization:

Has been acquired/merged with?:
N/A
Has had Spin-off?:
N/A
Has Had IPO?:
N/A
Year of IPO:
N/A
Has Patents?:
N/A
Number of Patents:
N/A
Total Sales to Date $:
$ 0.00
Total Investment to Date $
$ 0.00
POC Title:
N/A
POC Name:
N/A
POC Phone:
N/A
POC Email:
N/A
Narrative:
N/A

Award Totals:

Program/Phase Award Amount ($) Number of Awards
SBIR Phase I $548,563.00 5
SBIR Phase II $3,009,654.00 3

Award List:

Ultra-Dense Three-Dimensional Electronics for Space

Award Year / Program / Phase:
2008 / SBIR / Phase I
Award Amount:
$100,000.00
Agency / Branch:
DOD / USAF
Principal Investigator:
Abstract:
Tezzaron proposes the development of a 3D integrated memory on processor or host device. The proposed device is made from a very high-performance 3D integrated 512Mb DRAM memory device and a structured array with single layer customization. Both devices in the ultimate 3D integration have a high… More

3-D Space Qualifiable Field Programmable Gate Array

Award Year / Program / Phase:
2009 / SBIR / Phase I
Award Amount:
$100,000.00
Agency / Branch:
DOD / USAF
Principal Investigator:
Robert Patti, Systems Engineer
Abstract:
Tezzaron proposes to use its 3D wafer stacking technology to produce a true 3 dimensional fabric of programmable logic. A benefit of 3D integration is the fundamental increase in interconnect. FPGAs by their nature use huge amounts of interconnect and in normal 2D implementations, they often have an… More

Ultra-Dense Three-Dimensional Electronics for Space

Award Year / Program / Phase:
2009 / SBIR / Phase II
Award Amount:
$1,579,930.00
Agency / Branch:
DOD / USAF
Principal Investigator:
Abstract:
Chip-to-chip I/O has become a serious bottleneck, especially in communications between high-speed processors and their memory devices. Integrating a large amount of memory and a powerful processor into a single 3D-IC device could alleviate this problem. Bringing the memory on-chip with a very wide… More

Design and Fabrication Techniques for 3-Dimensional Integrated Circuits

Award Year / Program / Phase:
2009 / SBIR / Phase I
Award Amount:
$98,955.00
Agency / Branch:
DOD / DARPA
Principal Investigator:
Abstract:
Tezzaron proposes to use and extend its 3D wafer stacking technology to produce a 8Gb DRAM. The device will be made from 8 layers of memory and a single logic control layer, providing density far beyond the capability of current commercial technology. A device of this density can offer significant… More

Ultra-Dense Three-Dimensional Electronics for Space

Award Year / Program / Phase:
2009 / SBIR / Phase II
Award Amount:
$679,805.00
Agency:
DOD
Principal Investigator:
Abstract:
Two radiation hardened 3D integrated circuit memory devices will be fabricated under this effort. The 3D devices are created by the wafer level 3D bonding of separate silicon substrates. Within each of the ~200 die in the resultant wafer stack, there some 5 million vertical interconnects. The very… More

Radiation-Hardened, Resistive Random Access Memory

Award Year / Program / Phase:
2011 / SBIR / Phase I
Award Amount:
$99,997.00
Agency:
DOD
Principal Investigator:
Robert Patti, CTO – (630) 505-0404
Abstract:
ABSTRACT: Tezzaron intends to develop a nonvolatile low latency memory based on 3D assembly of RRAM memory cell wafers with CMOS logic wafers. The very high density 3D interconnect that Tezzaron can produce allows circuitry to be manufactured on different wafers in different semiconductor processes… More

Radiation-Hardened, Resistive Random Access Memory

Award Year / Program / Phase:
2012 / SBIR / Phase II
Award Amount:
$749,919.00
Agency:
DOD
Principal Investigator:
Robert Patti, CTO – (630) 505-0404
Abstract:
ABSTRACT: Tezzaron proposes to develop and demonstrate a 64Mb 3D integrated MRAM device comprising one non-volatile memory cell layer and one radiation hardened I/O logic and control layer. This memory device will address the industry"s next generation needs for nonvolatile memory density and… More

Next Generation Rad Hard Reduced Instruction Set Computer

Award Year / Program / Phase:
2014 / SBIR / Phase I
Award Amount:
$149,611.00
Agency / Branch:
DOD / USAF
Principal Investigator:
Robert Patti, CTO – (630) 505-0404
Abstract:
ABSTRACT: Tezzaron proposes to create a microprocessor device based on an ARM M0 processor designed to be fabricated in the Honeywell S150 Rad-Hard SOI semiconductor process. The device will be designed for both stand alone and 3D circuit integration. In a 3D application the device can be die to… More