Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
Agency / Branch:
DOD / DARPA
Tezzaron proposes to use and extend its 3D wafer stacking technology to produce a 8Gb DRAM. The device will be made from 8 layers of memory and a single logic control layer, providing density far beyond the capability of current commercial technology. A device of this density can offer significant improvements in system power, size, weight and performance. The major unknown in creating a device like this, are the issues that may arise when 3D integration is practiced beyond Tezzaron current devices of 3 or 4 tiers. In Phase I "dummy" wafers will be stacked to determine the feasibility of the planned 9 layer device to be fabricated as part of Phase II.
Small Business Information at Submission:
TEZZARON SEMICONDUCTOR CORP.
1415 Bond St. #111 Naperville, IL 60563
Number of Employees: