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Design and Fabrication Techniques for 3-Dimensional Integrated Circuits

Award Information

Agency:
Department of Defense
Branch:
Defense Advanced Research Projects Agency
Award ID:
91893
Program Year/Program:
2009 / SBIR
Agency Tracking Number:
09SB1-0146
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
Tezzaron Semiconductor Corp.
1415 Bond St. #111 Naperville, IL 60563-
View profile »
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 1
Fiscal Year: 2009
Title: Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
Agency / Branch: DOD / DARPA
Contract: W31P4Q-10-C-0012
Award Amount: $98,955.00
 

Abstract:

Tezzaron proposes to use and extend its 3D wafer stacking technology to produce a 8Gb DRAM. The device will be made from 8 layers of memory and a single logic control layer, providing density far beyond the capability of current commercial technology. A device of this density can offer significant improvements in system power, size, weight and performance. The major unknown in creating a device like this, are the issues that may arise when 3D integration is practiced beyond Tezzaron current devices of 3 or 4 tiers. In Phase I "dummy" wafers will be stacked to determine the feasibility of the planned 9 layer device to be fabricated as part of Phase II.

Principal Investigator:

Robert Patti
CTO
6305050404
rpatti@tezzaron.com

Business Contact:

Robert Patti
CTO
6305050404
rpatti@tezzaron.com
Small Business Information at Submission:

TEZZARON SEMICONDUCTOR CORP.
1415 Bond St. #111 Naperville, IL 60563

EIN/Tax ID: 841512428
DUNS: N/A
Number of Employees:
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No