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Networked System on a Chip for C4ISR

Award Information
Agency: Department of Defense
Branch: Army
Contract: W15P7T-04-C-J004
Agency Tracking Number: A032-2576
Amount: $120,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: A03-121
Solicitation Number: 2003.2
Timeline
Solicitation Year: 2003
Award Year: 2004
Award Start Date (Proposal Award Date): 2003-12-10
Award End Date (Contract End Date): 2004-06-09
Small Business Information
200 Greenleaf St.
Fort Worth, TX 76107
United States
DUNS: 008038846
HUBZone Owned: No
Woman Owned: Yes
Socially and Economically Disadvantaged: No
Principal Investigator
 Corey Clark
 Electrical Engineer
 (817) 872-1500
 corey.clark@williams-pyro.com
Business Contact
 Brent Williams
Title: Vice President
Phone: (817) 872-1500
Email: brent.williams@williams-pyro.com
Research Institution
N/A
Abstract

The overall goal of the Reconfigurable Networked Smart System on Chip (ReNSS) is to provide a network-oriented C4ISR chip. This will include designing (1) energy-efficient, intelligent sensor processing and fusion modules, (2) reconfigurable hardware for reliable communication and processing capabilities, (3) routing algorithms for a self-organizing network, and (4) an innovative fabrication method to combine these technologies onto a single energy-conservative VLSI chip. To advance the networking and C4ISR system capabilities further, this innovation can provide self-configuring, self-healing, fault-tolerant communications that also communicate with the fixed, wired network infrastructure. This hybrid network architecture enables sensors or C2 reporting and messaging functions to collect and process data both independently and cooperatively, as opposed to the centralized HOST data processing approach. The proposed solution focuses on reducing the latency of Network Reconfiguration in a distributed control infrastructure for component-level-based automation systems. It also will allow the creation of self-forming networks that can expand and contract on demand, extend into damaged areas with unknown infrastructures, and communicate between ad hoc elements as needed. Finally, the proposed effort will consider emerging automated tools for specification, design, implementation, testing, and verification for the chip design and development process.

* Information listed above is at the time of submission. *

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