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Company Information:

Name: Theseus Logic, Inc.
Address: 2500 Maitland Center Parkway, #203
Maitland, FL 32751-0146
Located in HUBZone: No
Woman-Owned: No
Minority-Owned: No
URL: N/A
Phone: (407) 282-9990

Award Totals:

Program/Phase Award Amount ($) Number of Awards
SBIR Phase I $537,231.00 6
SBIR Phase II $1,498,682.00 2

Award List:

N/A

Award Year / Program / Phase: 2000 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Dennis Ferguson, Director
Award Amount: $99,309.00

N/A

Award Year / Program / Phase: 2000 / SBIR / Phase II
Agency / Branch: DOD / USAF
Principal Investigator: Dennis Ferguson
Award Amount: $749,055.00

Testing Methodology/Tools for Asynchronous Circuits

Award Year / Program / Phase: 2002 / SBIR / Phase I
Agency / Branch: DOD / DARPA
Principal Investigator: Lief Sorensen, Senior Engineer
Award Amount: $98,937.00
Abstract:
"Theseus Logic intends to develop a test and verification tool and methodology that will provide the means to automatically insert testability into clockless circuits. Success in this endeavor will eliminate one of the remaining obstacles that hinderwidespread adoption of asynchronous design… More

Testing Methodology/Tools for Asynchronous Circuits

Award Year / Program / Phase: 2004 / SBIR / Phase II
Agency / Branch: DOD / DARPA
Principal Investigator: Lief Sorensen, Senior Engineer
Award Amount: $749,627.00
Abstract:
Theseus Logic, in partnership with FTL Systems, intends to integrate test and verification into their commercial design automation tool that will aid the designer by providing the means to automatically insert testability into clockless circuits. Success in this endeavor will eliminate one of the… More

Asynchronous Component Interconnect Protocol

Award Year / Program / Phase: 2004 / SBIR / Phase I
Agency / Branch: DOD / NAVY
Principal Investigator: John T. Filion, Engineering Manager
Award Amount: $69,443.00
Abstract:
Theseus Logic, Inc. proposes a plug and play peripheral interconnect protocol that protects against obsolescence by using an asynchronous approach that does not rely on a specific clock rate. Additionally, an asynchronous approach provides robustness and flexibility that allows the same protocol… More

Next Generation Programmable Gate Array

Award Year / Program / Phase: 2006 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Robert Read, Engineer
Award Amount: $99,991.00
Abstract:
Existing Field Programmable Gate Arrays (FPGAs) provide space-based users with an awkward choice between high performance commercial devices that are not capable of functioning reliably in a space-borne environment, or low performance devices that are specially hardened for space environments. This… More

WISS - Wireless, Intelligent Sensor System

Award Year / Program / Phase: 2006 / SBIR / Phase I
Agency: NASA
Principal Investigator: Michael S. Hagedorn, Principal Investigator
Award Amount: $69,554.00
Abstract:
Low power, robust communications protocols such as IEEE 802.15.4/Zigbee have made the concept of smart sensor networks attractive across many applications. These systems promise portable, networked, wireless, sensor suites capable of monitoring and controlling environments as needed. Theseus Logic… More

Low Power GPS Signal Acquisition Using Asynchronous Logic

Award Year / Program / Phase: 2006 / SBIR / Phase I
Agency / Branch: DOD / USAF
Principal Investigator: Michael Hagedorn, Senior Engineer
Award Amount: $99,997.00
Abstract:
Achieving a new military GPS capability based on direct acquisition of P(Y) and M codes requires massive parallel processing with large numbers of correlator channels (>1000) in the receiver searching for a code match. In synchronous systems the extensive clock tree required to support a… More