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Testing Methodology/Tools for Asynchronous Circuits

Award Information

Agency:
Department of Defense 		Branch:
Defense Advanced Research Projects Agency 		Award ID:
58452 		Program Year/Program:
2002 / SBIR
Agency Tracking Number:
02SB2-0328 		Solicitation Year:
N/A 		Solicitation Topic Code:
N/A 		Solicitation Number:
N/A
Small Business Information
Theseus Logic, Inc.
2500 Maitland Center Parkway, #203 Maitland, FL 32751-0146
View profile »
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 1
Fiscal Year: 2002
Title: Testing Methodology/Tools for Asynchronous Circuits
Agency / Branch: DOD / DARPA
Contract: DAAH0103CR045
Award Amount: $98,937.00
 

Abstract:

"Theseus Logic intends to develop a test and verification tool and methodology that will provide the means to automatically insert testability into clockless circuits. Success in this endeavor will eliminate one of the remaining obstacles that hinderwidespread adoption of asynchronous design approaches for DoD and commercial applications.Such circuits have been demonstrated to have commercially valuable properties, including high performance, low noise/low EMI, low power and easy circuit composability.This Phase I proposal will involve the initial development of the algorithms and approaches for the methodology/tool. Emphasis will be placed on maintaining compatibility with existing commercial EDA tools. The potential benefits of clockless design are legion: increased performance, better power management, reduced power rail noise, reduced radiated EMI, robust operation, ease of integration, and increased design reuse are but a few of the potentialbenefits that have been demonstrated by companies and researchers working in the field. Yet industry has failed to adopt clockless techniques in more than an exploratory fashion. Why? Electronic Design Automation (EDA) tool support for clockless designsare the main stumbling block today. The clockless industry is caught in a chicken-and-egg scenario. Industry will not adopt clockless technology until commercial grade design tools become available; yet commercial EDA companies will not develop

Principal Investigator:

Lief Sorensen
Senior Engineer
4075514698
lsorensen@theseus.com

Business Contact:

Ryan Jorgenson
VP Engineering
4075514703
ryan@theseus.com
Small Business Information at Submission:

Theseus Logic, Inc.
485 North Keller Road, Suite 140 Maitland, FL 32751

EIN/Tax ID: 411821836
DUNS: N/A
Number of Employees:
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No