Radiation-Hardened, Analog-to-Digital Converter with High-Bit Precision

ABSTRACT: Astronix Research Corp. proposes a novel pipeline ADC in 45nm CMOS SOI with 2GSPS sample rate and 62dB SNDR dynamic performance at 1/2 Nyquist rate (10 bits SNDR). The approach is based on extensive analysis and simulation showing that with properly optimized architecture and circuit topologies, as well as other proprietary methods, a single pipeline of only 3 stages can achieve over twice the resolution (+1 more bit) of the state of the art at this sample rate, and reduce power consumption almost 10 X, to under 500mW. The approach offers a foundation for single ADCs up to 20GSPS, and interleaved ADCs up to 80GSPS. The finished ADC would require a minimum of digital calibration. Ultra-deep submicron SOI technology combined with standard radiation-hardening-by-design techniques and a very small physical footprint are expected to achieve exceptional radiation tolerance for total dose, dose rate, SEU and SEL. A 45nm process CMOS node permits integration of ADC arrays into larger Systems on a Chip (SOC) for applications such QAM channel banks and beamforming receivers, offering substantially enhanced capabilities for high data-rate communications and signals collection. BENEFIT: A small form-factor/low power pipeline ADC has wide application for radar, beam forming antennas and communications systems in airborne and space systems. Systems of greater spectral diversity and higher sensitivity would be possible with the ADC. While State of the Art commercial parts from vendors such as E2v consume 5.7W each, the proposed effort seeks to deliver an ADC operating at power levels of approximately 0.5W (excluding other functions). As an example, because of substantial reductions in Size, Weight, and Power (SWAP) the proposed effort makes practical an array of over 20 ADCs on a single 5mm x 5mm silicon die operating at as little as 10W (excluding other functions) in a digitizer for a large, wideband channel bank. Compared to current SOA parts the proposed ADC would enable significantly improved QAM signaling with each ADC digitizing 800MHz bandwidth for a 20% oversampling over the Nyquist rate. The design would provide for improved data transmission with an error-corrected bit-rate at least 10 times higher than the bandwidth 20Gbps per channel. The small footprint and low power of the device will enable aggregations of ADCs enabling data throughput of 200Gbps. This level of data bandwidth would have enormous impact on all satellite communications allowing much higher system capabilities without increasing cost, weight or power consumption. At less than 1mm2 per ADC, the die size for the array of 20 ADCs could be as little as 5mm x 5mm, which is small by today"s standards. 10W of heat dissipation (not counting I/O power) is certainly feasible in this die size even without wafer thinning. Commercial products are now providing 6 or more serial photonic data channels of 20Gbps each, demonstrating the feasibility of such efforts and the potential for suitable I/O for integrated system development. In addition to the benefits for military satellite applications, commercial satellite communications could be significantly improved with devices of the capabilities and power consumption proposed. Beyond space-based applications, the proposed ADC is capable of improving a wide range of data communications applications. As only one commercial example, the ADCs would for the first time make possible small, less expensive home and business wireless networking devices capable of integrating multiple HD video streams in addition to conventional data traffic.