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Model Based FPGA Design Space Exploration and Optimization

Award Information

Agency:
Department of Defense
Branch:
N/A
Award ID:
Program Year/Program:
2011 / SBIR
Agency Tracking Number:
A2-4491
Solicitation Year:
2009
Solicitation Topic Code:
A09-131
Solicitation Number:
2009.3
Small Business Information
DETECCA COMMUNICATIONS, INC.
20271 Goldenrod Lane Suite 2008 Germantown, MD -
View profile »
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 2
Fiscal Year: 2011
Title: Model Based FPGA Design Space Exploration and Optimization
Agency: DOD
Contract: W31P4Q-11-C-0197
Award Amount: $676,271.00
 

Abstract:

Object-oriented hardware design techniques are gaining popularity as a means generate robust FPGA implementations. They potentially allow subject matter experts to convert high-level algorithms models directly into robust FPGA programs without the assistance of a hardware design specialist. Other potential benefits include increased productivity, reduced development costs, and fewer design errors. These model-based design techniques typically offer less efficient implementations and currently offer no means for the subject matter expert to tailor a design to meet specific size, weight, or power (SWAP) constraints. We propose a methodology that will provide the subject matter expert with FPGA Design Space Exploration and Optimization (DeSEO) capability in the domains of performance, power, and size. A meta-model, or object-oriented representation, of the algorithm will be used to provide a link between the high-level model and low-level FPGA implementation tools. Tobject-oriented hardware design techniques are gaining popularity as a means generate robust FPGA implementations. They potentially allow subject matter experts to convert high-level algorithms models directly into robust FPGA programs without the assistance of a hardware design specialist. Other potential benefits include increased productivity, reduced development costs, and fewer design errors. These model-based design techniques typically offer less efficient implementations and currently offer no means for the subject matter expert to tailor a design to meet specific size, weight, or power (SWAP) constraints. We propose a methodology that will provide the subject matter expert with FPGA Design Space Exploration and Optimization (DeSEO) capability in the domains of performance, power, and size. A meta-model, or object-oriented representation, of the algorithm will be used to provide a link between the high-level model and low-level FPGA implementation tools. This intermediate representation offers greater code portability while providing greater flexibility for design optimization and code generation.

Principal Investigator:

Michael Babst
President
(301) 977-5970
mspb@dsplogic.com

Business Contact:

Michael Babst
President
(301) 977-5970
mspb@dsplogic.com
Small Business Information at Submission:

DSPlogic, Inc.
13017 Wisteria Drive Suite 420 Germantown, MD -

EIN/Tax ID: 522276074
DUNS: N/A
Number of Employees:
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No