Transceiver ASIC for 100Gbps Detector Data Link
The Facility for Rare Isotope Beams (FRIB) employs extremely complex instrument, involving thousands of detector elements that generate unprecedented amount of experimental data. Reliable extremely high data throughput standard compliant interfaces that consume low power and are capable of operation under harsh radiation conditions of nuclear physics experiments are required. Pacific Microchip Corp. proposes to design a 100Gbps Ethernet (100GbE) transceiver ASIC that meets the requirements of the IEEE 802.3ba standard and MSA specifications and supports both fiber optic and non-standard 10m copper 4x25Gbps interfaces. The proposed ASIC will be designed using RadHard methods, novel low power techniques and will be capable to operate over a wide temperature range. A novel ASIC feature will improve flip- flop radiation hardness when necessary, by increasing flip-flop power. The ASIC will be fabricated using deep submicron latchup free SOI CMOS technology. In Phase I, the novel ASIC architecture will be developed and modeled, the critical circuits will be designed and in silico proof of the concept will be provided. Phase II will result in the ASICs prototype being ready for commercialization in Phase III. Commercial applications and other benefits: In addition to the primary application in the data interfaces of FRIB detectors and other nuclear physics instruments such as CMS and ATLAS at LHC, the proposed transceiver ASIC will find application in 100GbE modules and line cards (SMF and MMF media), DP-QPSK based long- haul single-wavelength 100GbE interfaces and low-cost low-power transmission of 4X25Gbps format data over 10m copper media for server inter/intro rack/cabinet interface.
Small Business Information at Submission:
Pacific Microchip Corp.
3916 Sepulveda Blvd. #108 Culver City, CA -
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