Modular, Rapid, Common Hardware-in-the-loop Framework Development
The Phase II technical objective of this project is to implement the technology conceived in Phase I into hardware prototypes that can be tested in an actual HWIL test lab environment. The developments and experience acquired in Phase I will be used to design and assemble a fully functional central switching unit, which in a WideBand Network is referred to as a network Concentrator. The goal of the Concentrator is to provide minimal latency, low jitter, and high bandwidth in a multi-node communication environment. Based on the research completed in Phase I, it is expected that a port-to-port latency of 20ns can be achieved. This delay would be roughly equivalent to the latency added by a four meter cable.
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