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SBIR Phase I: Analog/Mixed-Signal Integrated Circuit Verification Coverage

Award Information

Agency:
National Science Foundation
Branch:
N/A
Award ID:
Program Year/Program:
2013 / SBIR
Agency Tracking Number:
1248944
Solicitation Year:
2012
Solicitation Topic Code:
EI
Solicitation Number:
Small Business Information
Zipalog, Inc.
850 Central Parkway East Suite 160 Plano, TX 75074-5553
View profile »
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 1
Fiscal Year: 2013
Title: SBIR Phase I: Analog/Mixed-Signal Integrated Circuit Verification Coverage
Agency: NSF
Contract: 1248944
Award Amount: $150,000.00
 

Abstract:

This Small Business Innovation Research (SBIR) Phase I project proposes an analog verification coverage system. Today well-accepted formal and simulation-based techniques exist to capture and measure test coverage for digital integrated circuits, but there is no corresponding commercial capability for analog integrated circuits. Analog designers frequently spend much time analyzing and over-testing system behavior for a small set of well understood usage scenarios while leaving significant portions of the state-space completely untested. The design exploration problem for analog circuits presents critical challenges for implementing such a system due to the inherently large design space typical of analog circuits. The proposed innovative solution addresses this issue by determining the design space of relevance for a specific circuit and then assessing the completeness of exploration for that identified area. A prototype set of instruments will be delivered that measure coverage during analog/mixed-signal simulations. The proposed product will automatically parse the design netlist, add the instrumentation, run the user's existing simulator, analyze the output from the instrumentation, save data to a database, and build a coverage profile. This capability provides improved productivity and quality of results by eliminating redundant simulations and identifying areas of the design space that have not been sufficiently tested. The broader impact/commercial potential of this project is to improve the competitiveness of U.S. semiconductor industry by improving the quality of A/MS design verification, improving first pass design success and reducing time-to-market. The complexity of A/MS ASIC design has aggressively followed Moore's law, but innovations in design verification have not. More importantly the ideas being developed through this project have broader implications for complex systems that cross the boundaries between multiple domains and do not conform well to the highly constrained verification methods used for digital circuits. Multiple domain verification problems include integrated circuits used in combination with micro-electromechanical or opto-electronic devices, integrated circuits that are utilized in complex environments such as biomedical applications, as well as integrated circuits that are delivered in innovative forms rather than traditional packages where the verification of the entire delivery system is critical. Examples would include chips mounted directly on flexible substrates or contained within multi-chip modules that may include stacked die. To enable broad accessibility to small businesses as well as dispersed efforts such as geographically distributed design teams or research efforts, this capability can be delivered through an on-demand verification infrastructure being developed as part of an earlier project.

Principal Investigator:

Michael J. Krasnicki
2144183347
kraz@zipalog.com

Business Contact:

Michael J. Krasnicki
2144183347
kraz@zipalog.com
Small Business Information at Submission:

Zipalog, Inc.
850 Central Parkway East Suite 160 Plano, TX 75074-5553

EIN/Tax ID: 611648488
DUNS: N/A
Number of Employees:
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No