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High Speed Digitizer for Remote Sensing

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX14CP61P
Agency Tracking Number: 145484
Amount: $124,637.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: S1.02
Solicitation Number: N/A
Timeline
Solicitation Year: 2014
Award Year: 2014
Award Start Date (Proposal Award Date): 2014-06-20
Award End Date (Contract End Date): 2014-12-19
Small Business Information
2972 W Katapa Trail
Tucson, AZ 85742-4806
United States
DUNS: 078602532
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Esko Mikkola
 Principal Investigator
 (520) 647-4445
 engineering@alphacoreinc.com
Business Contact
 Esko Mikkola
Title: Business Official
Phone: (520) 647-4445
Email: engineering@alphacoreinc.com
Research Institution
 Stub
Abstract

Alphacore, Inc. proposes to design and characterize a 24Gsps (giga-samples per-second), 6-bit, low-power, and low-cost analog-to-digital converter (ADC) for use in a wide range of NASA's microwave sensor based remote sensing applications. The goal of this program is to provide an ultra-high-speed, low-power ADC that does both, provides excellent interfacing capabilities to top FPGAs and also has an optimized low-power spectrometer DSP backend available to be integrated on the same chip. The proposed ADC employs an innovative topology with high-bandwidth front-end sampling circuit combined with a flash-type ADC and encoder circuitry that simplifies FPGA interfacing. Innovative and effective digital calibration is used to guarantee spurious free Nyquist frequency band which is an important requirement in remote sensing applications.Comparable commercial ADCs are based on expensive and power-hungry bipolar transistor technologies such as indium phosphide (InP), gallium arsenide (GaAs) and silicon germanium (SiGe). Alphacore designs take advantage of the latest low-power, high-speed digital CMOS processes, resulting in ADC power consumption that is less than 1/8 of the power consumption of competitor ADCs. Using a CMOS process provides additional advantages in that we can leverage existing intellectual property (IP) to enhance the system-level integration of the ADC, e.g., on-chip digital calibration logic, data buffer memory, high-speed transceiver logic, and direct on-chip DSP capabilities.

* Information listed above is at the time of submission. *

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