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Company Information:

Company Name:
ALTERNATIVE SYSTEM CONCEPTS, INC.
Address:
22 Haverhill Road, P O Box 128
Windham, NH 03087
Phone:
(603) 437-2234
URL:
N/A
EIN:
20451753
DUNS:
619244395
Number of Employees:
6
Woman-Owned?:
No
Minority-Owned?:
No
HUBZone-Owned?:
No

Commercialization:

Has been acquired/merged with?:
N/A
Has had Spin-off?:
N/A
Has Had IPO?:
N/A
Year of IPO:
N/A
Has Patents?:
N/A
Number of Patents:
N/A
Total Sales to Date $:
$ 0.00
Total Investment to Date $
$ 0.00
POC Title:
N/A
POC Name:
N/A
POC Phone:
N/A
POC Email:
N/A
Narrative:
N/A

Award Totals:

Program/Phase Award Amount ($) Number of Awards
SBIR Phase I $503,143.00 9
SBIR Phase II $3,198,852.00 6

Award List:

BIST FOR OTS AND ASIC VLSI DESIGNS WITH VHDL

Award Year / Program / Phase:
1991 / SBIR / Phase I
Award Amount:
$54,234.00
Agency / Branch:
DOD / ARMY
Principal Investigator:
Carl A Karrfalt , Principal Investigator
Abstract:
N/a

BIST FOR OTS AND ASIC VLSI DESIGNS WITH VHDL

Award Year / Program / Phase:
1992 / SBIR / Phase II
Award Amount:
$424,000.00
Agency / Branch:
DOD / ARMY
Principal Investigator:
Carl A Karrfalt , Principal Investigator
Abstract:
The emergence of vlsi technology has increased the complexity of integrated circuit devices, in terms of transistors per device, at a rate multiplying by 100 every 10 years. new technologies, such as surface mount, require special techniques to make the boards testable. the goal of this research and… More

HARDWARE-SOFTWARE CO-DESIGN SUPPORTS INTEGRATED ENGINEERING

Award Year / Program / Phase:
1992 / SBIR / Phase I
Award Amount:
$54,300.00
Agency / Branch:
DOD / DARPA
Principal Investigator:
Carl Karrfalt
Abstract:
Phase i will explore novel ways to apply improved techniques using the ieee/ dod standard vhsic hardware description language (vhdl) to integrated engineering methods. in particular, it will enable hardware and software engineers to collaborate simultaneously during development of parallel computing… More

VIOOL PROVIDES CONCURRENT ENGINEERING SUPPORT FOR BUILDING ELECTRONIC SYSTEMS

Award Year / Program / Phase:
1993 / SBIR / Phase I
Award Amount:
$34,620.00
Agency:
DOC
Principal Investigator:
Casper B Stoel , Principal Investigator
Abstract:
N/a

VIOOL PROVIDES CONCURRENT ENGINEERING SUPPORT FOR BUILDING ELECTRONIC SYSTEMS

Award Year / Program / Phase:
1994 / SBIR / Phase II
Award Amount:
$199,967.00
Agency:
DOC
Principal Investigator:
Casper B Stoel , Principal Investigator
Abstract:
Concurrent engineering is a crucial methodology in reducing development cost and time of hardware and its complementing software. today no tools are available that can provide a tight integration of hardware and software development (co-design). asc proposes the development of viool (vhdl… More

VHDL Behavioral Synthesis Tool for Low Power Based on FRITS

Award Year / Program / Phase:
1995 / SBIR / Phase I
Award Amount:
$79,995.00
Agency / Branch:
DOD / USAF
Principal Investigator:
Seguei A. Sokolov
Abstract:
N/a

VHDL Behavioral Synthesis Tool for Low Power Based on FRITS

Award Year / Program / Phase:
1996 / SBIR / Phase II
Award Amount:
$749,889.00
Agency / Branch:
DOD / USAF
Principal Investigator:
Seguei A. Sokolov
Abstract:
Low power has been recently elevated to one of the most critical issues in circuit design, affecting circuit reliability, battery life, and heat sinking. In spite of this demand, surprisingly little support from CAD vendors exists for automated low power circuit design. Alternative System Concepts… More

SBIR Phase I: Boundary Scan and Board-Level Built-In-Self- Test Insertion into VHDL Designs with Commercial-off-the- Shelf Components

Award Year / Program / Phase:
1997 / SBIR / Phase I
Award Amount:
$74,995.00
Agency:
NSF
Principal Investigator:
Casper Stoel
Abstract:
N/a

Low Power Behavioral Synthesis For Control-Flow Intensive Hdl Designs

Award Year / Program / Phase:
1997 / SBIR / Phase I
Award Amount:
$69,999.00
Agency:
NASA
Principal Investigator:
Serguei Sokolov , DESIGN AUTOMATION ENGINEER
Abstract:
N/a

SBIR Phase I: Boundary Scan and Board-Level Built-In-Self- Test Insertion into VHDL Designs with Commercial-off-the- Shelf Components

Award Year / Program / Phase:
1998 / SBIR / Phase II
Award Amount:
$400,000.00
Agency:
NSF
Principal Investigator:
Casper Stoel
Abstract:
N/a

N/A

Award Year / Program / Phase:
2000 / SBIR / Phase I
Award Amount:
$65,000.00
Agency / Branch:
DOD / MDA
Principal Investigator:
Abstract:
N/a

N/A

Award Year / Program / Phase:
2000 / SBIR / Phase I
Award Amount:
$0.00
Agency / Branch:
DOD / ARMY
Principal Investigator:
Alex N. D. Zamfirescu
Abstract:
N/a

N/A

Award Year / Program / Phase:
2000 / SBIR / Phase II
Award Amount:
$749,996.00
Agency / Branch:
DOD / ARMY
Principal Investigator:
Alex N. D. Zamfirescu
Abstract:
N/a

Mitigation of Single Event Upset (SEU) by Virtual Redundancy in Design

Award Year / Program / Phase:
2001 / SBIR / Phase II
Award Amount:
$675,000.00
Agency / Branch:
DOD / MDA
Principal Investigator:
Robert MacDonald, Project Manger and CFO
Abstract:
Mitigation of Single Event Upset (SEU) to electronic devices and components has traditionally been and expensive problem to overcome. Dramatic improvements in electronics technology have rendered many prior SEU solutions ineffective and have created theneed for more advanced and innovative design… More

Rapid Radiation Failure Analysis of Digital Circuits Using a Computing Farm

Award Year / Program / Phase:
2003 / SBIR / Phase I
Award Amount:
$70,000.00
Agency / Branch:
DOD / MDA
Principal Investigator:
Alex Zamfirescu, Vice President Engineerin
Abstract:
The failure of digital circuits due to radiation using simulation was not addressed in the past due to several obstacles. First, radiation failure models, radiation faults dictionaries and the specification of susceptibility to radiation are not availablein the current hardware description languages… More