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Next-Generation Scalable Parallel Circuit Simulation for General Purpose…

Award Information

Agency:
Department of Defense
Branch:
Defense Advanced Research Projects Agency
Award ID:
28653
Program Year/Program:
1995 / SBIR
Agency Tracking Number:
28653
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
AMYRIS BIOTECHNOLOGIES
AMYRIS BIOTECHNOLOGIES 412 B KAINS AVE ALBANY, CA 94706 0126
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Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No
 
Phase 1
Fiscal Year: 1995
Title: Next-Generation Scalable Parallel Circuit Simulation for General Purpose Parallel Architectures
Agency / Branch: DOD / DARPA
Contract: N/A
Award Amount: $100,000.00
 

Abstract:

Circuit simulation is a critical bottleneck in design of complex VLSI chips. Even though clock speed and processing power of general purpose workstations are improving constantly, increases in size and complexity of VLSI chips indicates that this problem will only get worse. In the past, this problem has been addressed using special purpose hardware; example systems include the IBM Yorktown Simulation enginer, the Zycad XP simulation booster and FPGA based circuit emulators. These approaches require special purpose hardware and are expensive; they are also not inherently scalable. Perhaps the most promising approach is the use of general purpose, scalable, massively-parallel technology developed under the HPCC initiative for parallel execution of circuit simulation programs. Depending on circuit parameters, it is possible to get significant speedups from relatively inexpensive parallel architectures (e.g. multi-systems like the Thinking Machine CM5 and the Intel Paragon. The result of Phase I will be a detailed report outlining the technical methodology to be used to develop a next-generation parallel circuit simulator for general purpose parallel processing computers as well as detailing a productization strategy that will guarantee easy adoption within the EDA industry. ANTICIPATED BENEFITS: There is a great need within the EDA industry for new parallel processing simulation technology for general purpose parallel processing hardware. The proposed work will lead directly to a commercial simulation product.

Principal Investigator:

Rajeey Jain
3102063280

Business Contact:

Small Business Information at Submission:

Angeles Communications Design
21437 Mulholland Drive Woodland Hills, CA 91364

EIN/Tax ID:
DUNS: N/A
Number of Employees:
Woman-Owned: No
Minority-Owned: No
HUBZone-Owned: No