Thermal Management via Hybrid Wafers and Devices
79748S Silicon (Si) has been the workhorse of the electronics industry since the invention of the transistor, and engineers have found new ways to push the limits of processing speed and power handling ability of Si chips. Decreasing the gate lengths, increasing the number of processors per unit area, and increasing the clock speed has led to increasing the microprocessor computing power from 0.3 W in 1971 to nearly 100 W in 2000. Microprocessor power will likely exceed 1 kW by 2006. The high power loads consumed by the processors leads to the generation of a large amount of heat that must be transported away from the active area of the devices. This project will develop technology for integrating SiC power devices with Si drive circuitry in a hybrid power circuit that allows for increasing the power density of the devices while diverting the heat generated in the SiC circuits away from the less heat tolerant Si. The Si/SiC hybrid wafer will be comprised of a very thin Si membrane that has been sliced from a Si wafer and attached to a SiC wafer. Phase I will: (1) demonstrate circuit elements needed for a driver circuit on a bulk Si wafer, an SOI wafer, and hybrid Si/SiC, (2) bond a SiC power transistor to Si/SiC, SOI, and Si wafers, and (3) measure the electrical and thermal performance of the bonded SiC device on each substrate. Commercial Applications and Other Benefits as described by the awardee: The markets for wide band gap switches and radio frequency (RF) transistors are rapidly growing. The worldwide market for all power semiconductors was projected to increase by 8% in 2003 to $9.0 billion from $8.3 billion in 2002, out of which we estimate $2B is the total accessible market for SiC devices (rectifiers and switches) is estimated to be $2B.
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