ADVANCED GPS RECEIVER FOR SPACE APPLICATIONS

AN INNOVATIVE NEW RECEIVER ARCHITECTURE IS DESCRIBED IN THIS PROPOSAL FOR AN ADVANCED GPS RECEIVER DESIGN SUITABLE FOR SPACE APPLICATIONS. THE DESIGN ALLOWS FOR A SINGLE RECEIVER ARCHITECTURE TO BE EASILY ADAPTED FOR A VARIETY OF APPLICATIONS. THE AGR DESIGN PROPOSED INCLUDES THE CAPABILITY FOR HIGH-PRECISION SPACECRAFT NAVIGATION, TRACKING, ATTITUDE DETERMINATION, AND CAN BE EASILY ADAPTED TO IMPLEMENT A FAULT-TOLERANT GPS RECEIVER ARCHITECTURE. THE AGR DESIGN INCREASES THE RELIABILITY OF THE HARDWARE AND MINIMIZES THE RECEIVER SIZE THROUGH THE USE OF THE DIGITAL FRONT END (DFE) CHIP UNDER DEVELOPMENT BY JPL. A TRADE-STUDY WILL BE PERFORMED IN PHASE I ON THE RELATIVE MERITS OF PERFORMING THE GPS SIGNAL PROCESSING USING A CUSTOM GATE-ARRAY OR BY USING A HIGH SPEED MICROPROCESSOR. BENCHMARK TESTS PERFORMED BY NAVSYS HAVE DEMONSTRATED THAT THE I&O SIGNALS FROM A GPS RECEIVER CAN BE PROCESSED IN REAL-TIME USING CURRENT MICROPROCESSOR TECHNOLOGY. THE TRADE STUDY WILL RESOLVE WHETHER THE FIRMWARE OR SOFTWARE ARCHITECTURE WILL BEST MEET THE REQUIREMENTS OF FLEXIBILITY, ACCURACY, AND MINIMUM SIZE, WEIGHT, AND POWER. BASED ON THE RESULTS OF THE TRADE-STUDY, THE FINAL DESIGN FOR THE AGR WILL BE SELECTED AND A PROTOTYPE RECEIVER WILL BE CONSTRUCTED AND TESTED UNDER PHASE II. THE AGR DESIGN PROVIDES A HIGHLY FLEXIBLE RECEIVER ARCHITECTURE WHICH ALLOWS COMMON HARDWARE TO SERVE A WIDE VARIETY OF APPLICATIONS. BY TAKING ADVANTAGE OF RECENT TECHNOLOGY ADVANCES, THE SIZE AND WEIGHT OF THE RECEIVER HAVE BEEN REDUCED WITHOUT IMPACTING THE PERFORMANCE OR NUMBER OF CHANNELS. THE AGR DESIGN WILL BE IDEALLY SUITED TO MANY DOD AND COMMERCIAL SPACE PROGRAMS.