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High Speed RF Waveform Reader-Writer

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00014-06-M-0196
Agency Tracking Number: N064-029-0440
Amount: $70,000.00
Phase: Phase I
Program: STTR
Solicitation Topic Code: N06-T029
Solicitation Number: N/A
Solicitation Year: 2006
Award Year: 2006
Award Start Date (Proposal Award Date): 2006-08-01
Award End Date (Contract End Date): 2007-05-31
Small Business Information
15400 Calhoun Drive Suite 400
Rockville, MD 20855
United States
DUNS: 161911532
HUBZone Owned: No
Woman Owned: Yes
Socially and Economically Disadvantaged: No
Principal Investigator
 Eric van Doorn
 (301) 294-5229
Business Contact
 Mark James
Title: Contracts and Proposals M
Phone: (301) 294-5221
Research Institution
 Guy Schiavone
3100 Technology Parkway
Orlando, FL 32826
United States

 (407) 882-1300
 Nonprofit College or University

Intelligent Automation, Inc. (IAI), proposes a reliable integrated COTS-based reader/writer that can deliver RF waveforms to a cross-correlation based RF receiver at high speeds of 40 Gbps. We have already identified key COTS hardware that offers following advantages (1) input/ Output blocks of the FPGA can handle various input/ output standards like LVDS, LVCMOS, PCI-X, GTL and GTLP. Hence external COTS hardware delivering any of these voltage formats can be easily integrated (2) Options for reconfigurable logic and signal processing blocks (3) High speed expansion slots, 16 bit TX-RX interfaces with default LVDS support and number of prototyping interfaces, and (4) Low power consumption. The key innovations which we propose are (1) assembly of COTS hardware such as 1: 16 De-serializer and 16:1 Serializer, external memory blocks for data management (2) ability to perform test simulations on the FPGA itself, by creating HDL blocks (3) ability to read 10 Gword/s and store the data using FPGA control and (4) a clear transition plan to output 40 Gbps data per line using 4: 1 Multiplexing. The proposed system can be rapidly deployed for testing within the phase I base period. BENEFITS: The market for a IEEE compliant 40 Gbps per line circuit and accept 10 Gbps per line at data input and rewrite the data in the RAM units is quite large in fiber optic telecommunication network where digital data are be compressed in time and transmitted as bursts rather than time interleaved bit with other traffic. Such networks are also used on military platforms and bursted data may be significantly easier to handle than interleaved in multi-level security and priority networks such as during battle and high speed communication processing.

* Information listed above is at the time of submission. *

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