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Hybrid Tempertaure Heterogeneous Technology Energy-Efficient Digital Data Link

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N00014-13-C-0092
Agency Tracking Number: N11A-022-0407
Amount: $1,491,925.00
Phase: Phase II
Program: STTR
Solicitation Topic Code: N11A-T022
Solicitation Number: 2011.1
Solicitation Year: 2011
Award Year: 2013
Award Start Date (Proposal Award Date): 2013-01-30
Award End Date (Contract End Date): 2017-01-01
Small Business Information
175 Clearbrook Road
Elmsford, NY 10523-1109
United States
DUNS: 000000000
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Deepnarayan Gupta
 VP Research and Developme
 (914) 592-1190
Business Contact
 Steve Damon
Title: Assistant Controller
Phone: (914) 592-1190
Research Institution
 University of Massachusetts Amherst
 Carol Sprague
Research Administration Buildi 70 Butterfield Terrace
Amherst, MA 01003-9242
United States

 (413) 545-0698
 Federally Funded R&D Center (FFRDC)

HYPRES, in collaboration with University of Massachusetts, proposes an energy-efficient hybrid-temperature-heterogeneous-technology (HTHT) digital data link for interfacing 4K superconductor electronics with room-temperature electronics. Comprising several stages of cryogenic SiGe amplifiers at different temperatures, followed by equalization techniques, this data link will be designed to minimize the energy/bit figure-of-merit while exceeding the solicited specifications of 10^-12 bit-error rate (BER) at 30Gbps. Following simulation of the hybrid superconductor-semiconductor circuitry, a chain of three cryogenic SiGe integrated circuits (ICs) was designed and released for fabrication during Phase I. The estimated power consumption is 0.3 mW on the 4K stage. Upon testing these ICs in Phase I option, we plan to iteratively develop the cryogenic SiGe ICs and design the remaining semiconductor ICs which will operate at room temperature; a representative superconductor IC with differential output driver will also be iteratively developed. A major task in Phase II will be to build the HTHT data link by incorporating these ICs in their respective electronic modules and interconnecting them. The interconnect design uniquely combines electrical and thermal aspects and must be performed together with the IC design. Following the semiconductor and superconductor IC development, we will demonstrate the single channel and multi-channel data links.

* Information listed above is at the time of submission. *

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